Memory devices are disclosed. In an embodiment of the disclosed technology, a memory device may include a substrate including an active region, and a first floating gate, a second floating gate, a third floating gate and a fourth floating gate formed on the substrate, arranged to partially overlap with the active region. The first floating gate and the third floating gate are arranged in a first direction at one side of the active region and asymmetrical about a center of the active region, and the second floating gate and the fourth floating gate are arranged in the first direction at another side of the active region and asymmetrical about the center of the active region.

A memory cell has a first transistor and a second transistor. A drive circuit includes a boost circuit configured to generate a boost voltage on a boost line by boosting a predetermined reference voltage, and an adjustment circuit configured to adjust the boost voltage by drawing from the boost line an adjustment current commensurate with the boost voltage. The drive circuit feeds the adjusted boost voltage as the read voltage to the gates of the first and second transistors. In a read operation in which the read voltage is fed, the signal output circuit outputs a signal associated with a first value or a signal associated with a second value based on the drain currents in the first and second transistors.

A memory device is provided. The memory device includes a first transistor and a second transistor connected in series with the first transistor. The second transistor is programmable between a first state and a second state. A bit line connected to the second transistor. A sense amplifier connected to the bit line. The sense amplifier is operative to sense data from the bit line. A feedback circuit connected to the sense amplifier, wherein the feedback circuit is operative to control a bit line current of the bitline.

The present disclosure generally relates to circuit architectures for programming and accessing resistive change elements. The circuit architectures can program and access resistive change elements using neutral voltage conditions. The present disclosure also relates to methods for programming and accessing resistive change elements using neutral voltage conditions. The present disclosure additionally relates to sense amplifiers configurable into initializing configurations for initializing the sense amplifiers and comparing configurations for comparing voltages received by the sense amplifiers. The sense amplifiers can be included in the circuit architectures of the present disclosure.

For erasing four-terminal semiconductor Non-Volatile Memory (NVM) devices, we apply a high positive voltage bias to the control gate with source, substrate and drain electrodes tied to the ground voltage for moving out stored charges in the charge storage material to the control gate. For improving erasing efficiency and NVM device endurance life by lowering applied voltage biases and reducing the applied voltage time durations, we engineer the lateral impurity profile of the control gate near dielectric interface such that tunneling occurs on the small lateral region of the control gate near the dielectric interface. We also apply the non-uniform thickness of coupling dielectric between the control gate and the storage material for the NVM device such that the tunneling for the erase operation occurs within the small thin dielectric areas, where the electrical field in thin dielectric is the strongest for tunneling erase operation.

A three-way switch array structure including N first connectors, M second connectors, N×M third connectors and N×M three-way switches is provided, each three-way switch has a first terminal, a second terminal, a third terminal, a first switch and a second switch. Each of first terminals is disposed on one of the first connectors, each of second terminals is disposed on one of the second connectors, and each of third terminals is disposed on one of the third connectors, the first switch is disposed between the first terminal and the third terminal, and the second switch is disposed between the second terminal and the third terminal, wherein N and M are positive integers greater than or equal to 1.

Various embodiments of the present disclosure are directed towards an integrated chip including a first well region and a second well region disposed within a substrate. A gate electrode overlies the first well region and the second well region. A first memory active region is disposed within the second well region. A second memory active region is disposed within the second well region and is laterally offset from the first memory active region by a non-zero distance

Embodiments of counter-stress structures and methods for forming the same are disclosed. The present disclosure describes a semiconductor wafer including a substrate having a dielectric layer formed thereon and a device region in the dielectric layer. The device region includes at least one semiconductor device. The semiconductor wafer further includes a sacrificial region adjacent to the device region, wherein the sacrificial region includes at least one counter-stress structure configured to counteract wafer stress formed in the device region.

An ESD circuit includes a voltage division circuit, a RC control circuit and a voltage selection circuit. The voltage division circuit is connected between a first power pad and a first node, and generates a first voltage. The RC control circuit is connected between the first power pad and a second power pad, and generates a second voltage and a third voltage. The voltage selection circuit receives the first voltage and the second voltage, and outputs a fourth voltage. The first transistor and the second transistor are serially connected between the first power pad and the second power pad. A gate terminal of the first transistor receives the first voltage. A gate terminal of the second transistor receives the third voltage. The third transistor is connected with the first power pad and an internal circuit. A gate terminal of the third transistor receives the fourth voltage.

In accordance with an embodiment, a physically unclonable function device includes a set of transistor pairs, transistors of the set of transistor pairs having a randomly distributed effective threshold voltage belonging to a common random distribution; a differential read circuit configured to measure a threshold difference between the effective threshold voltages of transistors of transistor pairs of the set of transistor pairs, and to identify a transistor pair in which the measured threshold difference is smaller than a margin value as being an unreliable transistor pair; and a write circuit configured to shift the effective threshold voltage of a transistor of the unreliable transistor pair to be inside the common random distribution.