A semiconductor device including: a first level including memory control circuits (include a plurality of refresh circuits for the memory units) which include first transistors; a second level including a first array of memory cells including second transistors self-aligned to at least one of the third transistors; a third level disposed on top of the second level disposed on top of first level, the third level including a second array of memory cells including third transistors; a fourth level disposed on top of the third level, the fourth level including a third array of memory cells including fourth transistors, second level is bonded to the first level, a plurality of slits disposed through the second level, the third level, and the fourth level, the slits enable gate replacement of a plurality of the third transistors, where the second array of memory cells include a plurality of independently controlled memory units.

A semiconductor device, the device including: a first level including memory control circuits, the memory control circuits including first transistors, a second level disposed on top of the first level, the second level including a first array of memory cells including second transistors; a third level disposed on top of the second level, the third level including a second array of memory cells including third transistors; a fourth level disposed on top of the third level, the fourth level including a third array of memory cells including fourth transistors, where the second level is bonded to the first level, where the memory control circuits include cache memory, and where the second array of memory cells include a plurality of independently controlled memory units, and a plurality of refresh circuits for the memory units.

A non-volatile memory device includes a plurality of non-volatile memory cell, a body oxide layer, and a well layer above the body oxide layer and has a doped type of a first type. Each non-volatile memory cell includes first to third doped regions within the well layer, a select gate structure and a memory gate structure. The third doped region includes a first portion and a second portion. The select gate structure is formed above the well layer and between the first and second doped regions. The memory gate structure is formed above the well layer and between the second and third doped regions. The first portion of the third doped region has a doped type of the first type, and the first and second doped regions and the second portion of the third doped region have a doped type of a second type different from the first type.