Apparatuses and techniques are described for detecting and isolating defective blocks of memory cells in a multi-plane operation such as program or erase. In one aspect, a program operation begins in a multi-plane mode, for one block in each plane. If fewer than all blocks complete programming by the time a trigger number of program loops have been performed, one or more unpassed blocks are programmed further, one at a time, in a single plane mode. If the one or more unpassed blocks do not complete programming when a maximum allowable number of program loops have been performed, they are marked as bad blocks and disabled from further operations. In another aspect, when a trigger number of program loops have been performed, one or more unpassed blocks are subject to a word line leakage detection operation.

A memory device includes unselected sub-block, which includes bit line; drain select (SGD) transistor coupled with bit line; a source voltage line; source select (SGS) transistor coupled with source voltage; and wordlines coupled with gates of string of cells, which have channel coupled between the SGS/SGD transistors. Control logic coupled with unselected sub-block is to: cause the SGD/SGS transistors to turn on while ramping the wordlines from a ground voltage to a pass voltage associated with unselected wordlines in preparation for read operation; cause, while ramping the wordlines, the channel to be pre-charged by ramping voltages on the bit line and the source voltage line to a target voltage that is greater than a source read voltage level; and in response to wordlines reaching the pass voltage, causing the SGD and SGS transistors to be turned off, to leave the channel pre-charged to the target voltage during the read operation.

A memory device including a plurality of memory cells, a peripheral circuit, and control logic. The peripheral circuit is configured to generate a plurality of operating voltages used in a memory operation, based on a target pump clock, and perform the memory operation by using the plurality of operating voltages. The control logic is configured to select the target pump clock among a plurality of pump clocks, based on a number of data bits which selected memory cells on which the memory operation is to be performed among the plurality of memory cells store, and control the peripheral circuit to perform the memory operation on the selected memory cells.

The present disclosure provides a method of data protection for a NAND memory. The method can include programming a selected page of the NAND flash memory device according to programming data. The programming of the selected page can include a plurality of programming operations and a plurality of verifying operations, with ones of the plurality of verifying operations performed after corresponding ones of the plurality of programming operations to determine whether programmed memory cells of the selected page have threshold voltage levels according to the programming data. The method can also include determining a completion of the programming of the selected page based on each of the plurality of verification operations returning a pass result. The method can also include performing, after the determining, a read operation on the selected page by the NAND flash memory device to self-verify data stored at the selected page according to the programming data.

The present disclosure provides a method for debugging of flash memory devices using NAND self-verification The method can include programming a selected page of the NAND flash memory device according to first and second programming data. The selected page can include a plurality of memory cells corresponding to a word line. The programming of the selected page can include a plurality of programming operations and a plurality of verifying operations. Ones of the plurality of verifying operations can be performed after corresponding ones of the plurality of programming operations to determine whether programmed memory cells of the selected page have threshold voltage levels according to the first or second programming data The method can also include performing self-verification on the selected page to determine whether data stored at the selected page was overwritten and generating a fail indication upon determining that the data stored at the selected page was overwritten.

To increase the speed of programming of a multi-plane non-volatile memory, it is proposed to accelerate the programming of the last one or more data states for one or more slow planes.

A method includes determining that a ratio of valid data portions to a total quantity of data portions of a block of memory cells is greater than or less than a valid data portion threshold and determining that health characteristics for the valid data portions of the block of memory cells are greater than or less than a valid data health characteristic threshold. The method further includes performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is greater than the valid data portion threshold and performing a second media management operation on at least a portion of the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is less than the valid data portion threshold and the health characteristics for the valid data portions are greater than the valid data health characteristic threshold.

A semiconductor memory device includes a memory cell array, a memory apparatus and a power-on operation apparatus, and is capable of knowing whether a reading of the setting information which is set during the power-on operation had been completed correctly or not. The flash memory reads the fuse memory when it is detected that the power supply has reached the power-on detection level, and determines whether the reading of the fuse memory had been completed correctly. When not completed correctly, the fuse memory is read again within the maximum read count, and the setting information (which was read from the fuse memory) is written into the CF register. The identification information (that identifies whether the reading of the fuse memory has been completed correctly or not) is stored in the register.

The present disclosure relates to a method for accessing an array of memory cells, including storing a set of user data in a plurality of memory cells, storing, in a portion of the array, additional information representative of a voltage difference between a first threshold voltage and a second threshold voltage of the memory cells programmed to a first logic state, applying to the array a read voltage to activate a first group of memory cells corresponding to a preset number of memory cells, determining that the first group of memory cells has been activated based on applying the read voltage, wherein the read voltage is equal to the first threshold voltage when the first group of memory cells has been activated, and based on the additional data information, applying the voltage difference to the array to activate a second group of memory cells programmed to the first logic state.

A memory device including a plurality of memory cells, configured to perform a read operation of reading data from memory cells connected to a selected word line, and configured to apply a plurality of read voltages to the selected word line, apply a first pass voltage to unselected word lines while first read voltages for determining a program state of memory cells having a threshold voltage higher than a reference voltage among the plurality of read voltages are applied to the selected word line, and apply a second pass voltage higher than the first pass voltage to the unselected word line while second read voltages for determining a program state of memory cells having a threshold voltage lower than the reference voltage among the plurality of read voltages are applied to the selected word line.