When programming and verifying a memory device which includes a plurality of memory cells and a plurality of word lines, a first coarse programming is first performed on a first memory cell among the plurality of memory cells which is controlled by a first word line among the plurality of word lines, and then a second coarse programming is performed on a second memory cell among the plurality of memory cells which is controlled by a second word line among the plurality of word lines. Next, a first coarse verify current is used for determining whether the first memory cell passes a coarse verification and a second coarse verify current is used for determining whether the second memory cell passes a second coarse verification, wherein the second coarse verify current is smaller than the first coarse verify current.

When programming and verifying a memory device which includes a plurality of memory cells and a plurality of word lines, a first coarse programming is first performed on a first memory cell among the plurality of memory cells which is controlled by a first word line among the plurality of word lines, and then a second coarse programming is performed on a second memory cell among the plurality of memory cells which is controlled by a second word line among the plurality of word lines. Next, a first coarse verify current is used for determining whether the first memory cell passes a coarse verification and a second coarse verify current is used for determining whether the second memory cell passes a second coarse verification, wherein the second coarse verify current is smaller than the first coarse verify current.

Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a method is provided for programming a memory device having a plurality of memory chips that comprise multiple-level-cells. The method includes loading first data in a first chip, programming the first data into selected cells of the first chip using a single-level-cell (SLC) programming mode, and reprogramming the first data stored in the selected cells of the first chip to other cells of the first chip using a multiple-level-cell programming mode. The method also includes repeating the operations of loading, programming, and reprogramming for the remaining chips. The loading operations for the remaining chips begin at the completion of the loading operation for the first chip and occur in a non-overlapping sequential manner, and the loading operations for the remaining chips are performed in parallel with the programming and reprogramming operations of the first chip.

Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a method is provided for programming a memory device having a plurality of memory chips that comprise multiple-level-cells. The method includes loading first data in a first chip, programming the first data into selected cells of the first chip using a single-level-cell (SLC) programming mode, and reprogramming the first data stored in the selected cells of the first chip to other cells of the first chip using a multiple-level-cell programming mode. The method also includes repeating the operations of loading, programming, and reprogramming for the remaining chips. The loading operations for the remaining chips begin at the completion of the loading operation for the first chip and occur in a non-overlapping sequential manner, and the loading operations for the remaining chips are performed in parallel with the programming and reprogramming operations of the first chip.

Numerous examples of summing circuits for a neural network are disclosed. In one example, a circuit for summing current received from a plurality of synapses in a neural network comprises a voltage source; a load coupled between the voltage source and an output node; a voltage clamp coupled to the output node for maintaining a voltage at the output node; and a plurality of synapses coupled between the output node and ground; wherein an output current flows through the output node, the output current equal to a sum of currents drawn by the plurality of synapses.

Numerous examples of summing circuits for a neural network are disclosed. In one example, a circuit for summing current received from a plurality of synapses in a neural network comprises a voltage source; a load coupled between the voltage source and an output node; a voltage clamp coupled to the output node for maintaining a voltage at the output node; and a plurality of synapses coupled between the output node and ground; wherein an output current flows through the output node, the output current equal to a sum of currents drawn by the plurality of synapses.

A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages before a ready/busy signal changing from a ready state to a busy state.

A memory device can include a nonvolatile memory (NVM) cell array, data path circuits, coupled between the NVM cell array and an output of the device, that are configured to enable access to the NVM cell array via a plurality of bit lines. A first charge pump can generate a first voltage supply. A second charge pump can generate a second voltage supply. Switch circuits are configured to, in a first mode, couple the first voltage supply to data path circuits, and in a second mode, couple the second voltage supply to the data path circuits. The first charge pump, the second charge pump, the switch circuits, the data path circuits and the NVM cell array are formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.

A memory device can include a nonvolatile memory (NVM) cell array, data path circuits, coupled between the NVM cell array and an output of the device, that are configured to enable access to the NVM cell array via a plurality of bit lines. A first charge pump can generate a first voltage supply. A second charge pump can generate a second voltage supply. Switch circuits are configured to, in a first mode, couple the first voltage supply to data path circuits, and in a second mode, couple the second voltage supply to the data path circuits. The first charge pump, the second charge pump, the switch circuits, the data path circuits and the NVM cell array are formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.

A non-volatile memory device comprises a memory cell region including a plurality of cell transistors, a first-type semiconductor substrate including a peripheral circuit region including circuits configured to control the plurality of cell transistors, and a plurality of pass transistors on the peripheral circuit region of the semiconductor substrate, wherein the peripheral circuit region includes a first region and a second region which are doped to a depth at an upper portion of the semiconductor substrate while being insulated from each other by an implant region, wherein the first region is a second type different from the first type, and includes a first doped region, and a first well region beneath the first doped region and configured to have a higher doping concentration than the first doped region, wherein the second region is the first type, and includes a second doped region, and a second well region beneath the second doped region and configured to have a higher doping concentration than the second doped region, wherein a first pass transistor on the first region from among the plurality of pass transistors is connected to a string selection line or a ground selection transistor, wherein a second pass transistor on the second region from among the plurality of pass transistors is connected to a word line, wherein a positive voltage or a negative voltage is configured to be applied to the second well region during operation of the second pass transistor.