A non-volatile memory device comprises a memory cell region including a plurality of cell transistors, a first-type semiconductor substrate including a peripheral circuit region including circuits configured to control the plurality of cell transistors, and a plurality of pass transistors on the peripheral circuit region of the semiconductor substrate, wherein the peripheral circuit region includes a first region and a second region which are doped to a depth at an upper portion of the semiconductor substrate while being insulated from each other by an implant region, wherein the first region is a second type different from the first type, and includes a first doped region, and a first well region beneath the first doped region and configured to have a higher doping concentration than the first doped region, wherein the second region is the first type, and includes a second doped region, and a second well region beneath the second doped region and configured to have a higher doping concentration than the second doped region, wherein a first pass transistor on the first region from among the plurality of pass transistors is connected to a string selection line or a ground selection transistor, wherein a second pass transistor on the second region from among the plurality of pass transistors is connected to a word line, wherein a positive voltage or a negative voltage is configured to be applied to the second well region during operation of the second pass transistor.

Memory might include a controller configured to cause the memory to capacitively couple a first voltage level from a voltage node to a node of a sense circuit, selectively discharge the node of the sense circuit through a memory cell, measure a current demand of the voltage node while selectively discharging the node of the sense circuit through the memory cell, determine a second voltage level in response to the measured current demand, isolate the node of the sense circuit from the memory cell, capacitively couple the second voltage level from the voltage node to the node of the sense circuit, and determine a data state of the memory cell in response to a voltage level of the node of the sense circuit while capacitively coupling the second voltage level to the node of the sense circuit.

Memory might include a controller configured to cause the memory to capacitively couple a first voltage level from a voltage node to a node of a sense circuit, selectively discharge the node of the sense circuit through a memory cell, measure a current demand of the voltage node while selectively discharging the node of the sense circuit through the memory cell, determine a second voltage level in response to the measured current demand, isolate the node of the sense circuit from the memory cell, capacitively couple the second voltage level from the voltage node to the node of the sense circuit, and determine a data state of the memory cell in response to a voltage level of the node of the sense circuit while capacitively coupling the second voltage level to the node of the sense circuit.

Methods of operating a memory, and memories having a controller configured to cause the memory to perform such methods, include applying a plurality of first voltage levels to an access line, applying a plurality of second voltage levels to a control gate of a string driver connected to the access line for a first portion of the plurality of first voltage levels with each second voltage level of the plurality of second voltage levels being greater than a respective first voltage level by a first voltage differential, and applying a plurality of third voltage levels to the control gate of the string driver for a second portion of the plurality of first voltage levels with each third voltage level of the plurality of third voltage levels being greater than a respective first voltage level by a second voltage differential less than the first voltage differential.

Methods of operating a memory, and memories having a controller configured to cause the memory to perform such methods, include applying a plurality of first voltage levels to an access line, applying a plurality of second voltage levels to a control gate of a string driver connected to the access line for a first portion of the plurality of first voltage levels with each second voltage level of the plurality of second voltage levels being greater than a respective first voltage level by a first voltage differential, and applying a plurality of third voltage levels to the control gate of the string driver for a second portion of the plurality of first voltage levels with each third voltage level of the plurality of third voltage levels being greater than a respective first voltage level by a second voltage differential less than the first voltage differential.

A memory device includes a memory cell array configured to store data, a control circuit configured to control the memory cell array in response to a command; and a receiver configured to be placed in an active state based on a first signal, a second signal, or an operation result of an address and the command, and be enabled to receive a command or data.

A memory device includes a memory cell array configured to store data, a control circuit configured to control the memory cell array in response to a command; and a receiver configured to be placed in an active state based on a first signal, a second signal, or an operation result of an address and the command, and be enabled to receive a command or data.

The present invention relates to a flash memory device that uses strap cells in a memory array of non-volatile memory cells as source line pull down circuits. In one embodiment, the strap cells are erase gate strap cells. In another embodiment, the strap cells are source line strap cells. In another embodiment, the strap cells are control gate strap cells. In another embodiment, the strap cells are word line strap cells.

The present invention relates to a flash memory device that uses strap cells in a memory array of non-volatile memory cells as source line pull down circuits. In one embodiment, the strap cells are erase gate strap cells. In another embodiment, the strap cells are source line strap cells. In another embodiment, the strap cells are control gate strap cells. In another embodiment, the strap cells are word line strap cells.

A memory device includes pages, each being composed of a plurality of memory cells arrayed on a substrate in row form, and controls voltages to be applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer of each of the memory cells included in the pages to perform a page write operation of holding a hole group generated by an impact ionization phenomenon or a gate induced drain leakage current in a channel semiconductor layer, and controls voltages to be applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the fourth gate conductor layer, the first impurity layer, and the second impurity layer to perform a page erase operation of removing the hole group out of the channel semiconductor layer. The first impurity layer of the each of the memory cells is connected to a source line, the second impurity layer is connected to a bit line, one of the first gate conductor layer and the second gate conductor layer is connected to one of word lines, and the other is connected to a first driving control line. The first driving control line is provided in common for adjacent ones of the pages, and when in the page erase operation, the memory device applies pulsed voltages to one of the word lines which performs the page erase operation and the first driving control line, and applies a fixed voltage to another one of the word lines which is not selected to perform the page erase operation.