A memory device includes pages, each being composed of a plurality of memory cells arrayed on a substrate in row form, and controls voltages to be applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer of each of the memory cells included in the pages to perform a page write operation of holding a hole group generated by an impact ionization phenomenon or a gate induced drain leakage current in a channel semiconductor layer, and controls voltages to be applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the fourth gate conductor layer, the first impurity layer, and the second impurity layer to perform a page erase operation of removing the hole group out of the channel semiconductor layer. The first impurity layer of the each of the memory cells is connected to a source line, the second impurity layer is connected to a bit line, one of the first gate conductor layer and the second gate conductor layer is connected to one of word lines, and the other is connected to a first driving control line. The first driving control line is provided in common for adjacent ones of the pages, and when in the page erase operation, the memory device applies pulsed voltages to one of the word lines which performs the page erase operation and the first driving control line, and applies a fixed voltage to another one of the word lines which is not selected to perform the page erase operation.

In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

A memory system includes a memory device and a memory controller. The memory device includes a memory cell array configured to store data, a data input and output interface configured to receive a command, an address, and data to be written into the memory cell array from the memory controller, and to output data read from the memory cell array to the memory controller, and a control circuit configured to control the memory cell array to perform an operation in response to receipt of a command while a first control signal is being asserted by the memory controller and receipt of an address subsequent to the command while a second control signal is being asserted by the memory controller.

A memory system includes a memory device and a memory controller. The memory device includes a memory cell array configured to store data, a data input and output interface configured to receive a command, an address, and data to be written into the memory cell array from the memory controller, and to output data read from the memory cell array to the memory controller, and a control circuit configured to control the memory cell array to perform an operation in response to receipt of a command while a first control signal is being asserted by the memory controller and receipt of an address subsequent to the command while a second control signal is being asserted by the memory controller.

Apparatus might include a controller configured to cause the apparatus to program a plurality of memory cells from a first data state to a second data state higher than the first data state, determine a respective first voltage level of a control gate voltage deemed to cause each memory cell of a first and second subset of memory cells of the plurality of memory cells to reach the second data state, determine a respective second voltage level of a control gate voltage deemed sufficient to cause each memory cell of the first subset of memory cells to reach a third data state higher than the second data state, and determine a respective second voltage level of a control gate voltage deemed sufficient to cause each memory cell of the second subset of memory cells to reach a fourth data state higher than the third data state.

Apparatus might include a controller configured to cause the apparatus to program a plurality of memory cells from a first data state to a second data state higher than the first data state, determine a respective first voltage level of a control gate voltage deemed to cause each memory cell of a first and second subset of memory cells of the plurality of memory cells to reach the second data state, determine a respective second voltage level of a control gate voltage deemed sufficient to cause each memory cell of the first subset of memory cells to reach a third data state higher than the second data state, and determine a respective second voltage level of a control gate voltage deemed sufficient to cause each memory cell of the second subset of memory cells to reach a fourth data state higher than the third data state.

A program method includes applying a first voltage to a plurality of bit lines, applying a second voltage to a common source line (CSL), and performing a program loop by applying a program voltage and a verify voltage to each of a plurality of ground selection lines (GSLs) positioned between one bit line among the plurality of bit lines and the CSL. The program loop is performed on both a program completed cell in which a program is completed by applying the program voltage and a program target cell.

Described are systems and methods for reducing maximum programming voltage in memory programming operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying one or more memory cells for performing a memory programming operation, wherein the memory cells are electrically coupled to a target wordline and one or more target bitlines; causing drain-side select gates and source-side select gates of the memory array to be turned off; causing unselected wordlines of the memory array to discharge to a predefined voltage level; and causing one or more programming voltage pulses to be applied to the target wordline.

Described are systems and methods for reducing maximum programming voltage in memory programming operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying one or more memory cells for performing a memory programming operation, wherein the memory cells are electrically coupled to a target wordline and one or more target bitlines; causing drain-side select gates and source-side select gates of the memory array to be turned off; causing unselected wordlines of the memory array to discharge to a predefined voltage level; and causing one or more programming voltage pulses to be applied to the target wordline.