A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.

A circuit for adjusting a select gate voltage of a non-volatile memory is provided. The circuit includes a well, a select gate, and an adjustment unit. There is a capacitive coupling between the well and the select gate. The adjustment unit generates a driving voltage for the select gate based on a non-constant voltage.

A circuit for adjusting a select gate voltage of a non-volatile memory is provided. The circuit includes a well, a select gate, and an adjustment unit. There is a capacitive coupling between the well and the select gate. The adjustment unit generates a driving voltage for the select gate based on a non-constant voltage.

Apparatus might include an array of memory cells and a controller to perform access operations on the array of memory cells. The controller might be configured to establish a negative potential in a body of a memory cell of the array of memory cells, and initiate a sensing operation on the memory cell while the body of the memory cell has the negative potential. Apparatus might further include an array of memory cells, a timer, and a controller to perform access operations on the array of memory cells. The controller might be configured to advance the timer, and establish a negative potential in a body of a memory cell of the array of memory cells in response to a value of the timer having a desired value.

Apparatus might include an array of memory cells and a controller to perform access operations on the array of memory cells. The controller might be configured to establish a negative potential in a body of a memory cell of the array of memory cells, and initiate a sensing operation on the memory cell while the body of the memory cell has the negative potential. Apparatus might further include an array of memory cells, a timer, and a controller to perform access operations on the array of memory cells. The controller might be configured to advance the timer, and establish a negative potential in a body of a memory cell of the array of memory cells in response to a value of the timer having a desired value.

A determination that a first programming operation has been performed on a particular memory cell can be made. A determination can be made, based on one or more threshold criteria, whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.

A determination that a first programming operation has been performed on a particular memory cell can be made. A determination can be made, based on one or more threshold criteria, whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.

Apparatus having a controller configured to connect a string of series-connected memory cells (e.g., a NAND string) to a node, perform a sensing operation on a selected memory cell of the NAND string while the selected memory cell is connected to the node through a first field-effect transistor (FET) between the node and the NAND string and through a second FET between the first FET and the NAND string, connect a control gate of the first FET to receive a lower voltage level after performing the sensing operation, connect the control gate of the second FET to receive the lower voltage level after connecting the control gate of the first FET to receive the lower voltage level, and connect a control gate of the selected memory cell to receive the lower voltage level after connecting the control gate of the second FET to receive the lower voltage level.

Apparatus having a controller configured to connect a string of series-connected memory cells (e.g., a NAND string) to a node, perform a sensing operation on a selected memory cell of the NAND string while the selected memory cell is connected to the node through a first field-effect transistor (FET) between the node and the NAND string and through a second FET between the first FET and the NAND string, connect a control gate of the first FET to receive a lower voltage level after performing the sensing operation, connect the control gate of the second FET to receive the lower voltage level after connecting the control gate of the first FET to receive the lower voltage level, and connect a control gate of the selected memory cell to receive the lower voltage level after connecting the control gate of the second FET to receive the lower voltage level.

A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.