CIRCUIT AND METHOD FOR ADJUSTING SELECT GATE VOLTAGE OF NON-VOLATILE MEMORY DURING ERASURE OF MEMORY CELLS BASED ON A WELL VOLTAGE

Abstract

A circuit for adjusting a select gate voltage of a non-volatile memory is provided. The circuit includes a well, a select gate, and an adjustment unit. There is a capacitive coupling between the well and the select gate. The adjustment unit generates a driving voltage for the select gate based on a non-constant voltage.

Claims

1. A circuit for adjusting a select gate voltage of a non-volatile memory, comprising: a well; a select gate, wherein there is a capacitive coupling between the well and the select gate; and an adjustment unit generating a driving voltage for the select gate based on a non-constant voltage.

2. The circuit of claim 1, wherein the non-constant voltage is a voltage of the well.

3. The circuit of claim 2, wherein the adjustment unit directly outputs the voltage of the well as the driving voltage.

4. The circuit of claim 2, wherein the adjustment unit reduces the voltage of the well to generate the driving voltage.

5. The circuit of claim 4, wherein the adjustment unit comprises: a voltage divider, coupled between the select gate and the well, outputting a fraction of the voltage of the well as the driving voltage.

6. The circuit of claim 4, wherein the adjustment unit comprises: at least one diode coupled in series between the well and the select gate to reduce the voltage of the well.

7. A method for adjusting a select gate voltage of a non-volatile memory, wherein there is a capacitive coupling between a well and a select gate of the non-volatile memory, the method comprising: generating a driving voltage by using an adjustment unit; and conducting the driving voltage to the select gate.

8. The method of claim 7, wherein the step of generating the driving voltage is based on a non-constant voltage, and the non-constant voltage is a voltage of the well.

9. The method of claim 8, wherein the step of generating the driving voltage comprises: directly outputting the voltage of the well as the driving voltage.

10. The method of claim 8, wherein the step of generating the driving voltage comprises: reducing the voltage of the well to generate the driving voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0022] FIG. 1 is a schematic diagram showing a part of a conventional NAND string.

[0023] FIG. 2 is a schematic diagram showing a part of a conventional NAND flash memory.

[0024] FIG. 3 is a timing diagram showing some voltage signals in the circuit in FIG. 2.

[0025] FIG. 4 and FIG. 5 are schematic diagrams showing a circuit for adjusting select gate voltage for an erase operation of a non-volatile memory according to two embodiments of the present invention.

[0026] FIG. 6 is a timing diagram showing some voltage signals in the circuit in FIG. 5 according to an embodiment of the present invention.

[0027] FIG. 7 is a schematic diagram showing a circuit for adjusting select gate voltage for an erase operation of a non-volatile memory according to an embodiment of the present invention.

[0028] FIG. 8 is a timing diagram showing some voltage signals in the circuit in FIG. 7 according to an embodiment of the present invention.

[0029] FIG. 9 is a schematic diagram showing a circuit for adjusting select gate voltage for an erase operation of a non-volatile memory according to an embodiment of the present invention.

[0030] FIG. 10 is a timing diagram showing some voltage signals in the circuit in FIG. 9 according to an embodiment of the present invention.

[0031] FIG. 11 is a schematic diagram showing a circuit for adjusting select gate voltage for an erase operation of a non-volatile memory according to an embodiment of the present invention.

[0032] FIG. 12 is a timing diagram showing some voltage signals in the circuit in FIG. 11 according to an embodiment of the present invention.

DESCRIPTION OF THE EMBODIMENTS

[0033] Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0034] FIG. 4 is a schematic diagram showing a circuit 400 for adjusting select gate voltage for an erase operation of a non-volatile memory according to an embodiment of the present invention. The circuit 400 includes a p-well PWI, a select gate SSL, a pass transistor 406, an adjustment unit 404, and switches 402 and 403. The pass transistor 406 is coupled to the select gate SSL. The adjustment unit 404 is coupled to the p-well

[0035] PWI. The switch 402 is coupled between the pass transistor 406 and the adjustment unit 404. The switch 403 is coupled to the pass transistor 406.

[0036] In this embodiment, the non-volatile memory is a NAND flash memory. The select gate SSL and the p-well PWI is a part of a NAND string of the NAND flash memory. The capacitor 408 represents the capacitive coupling between the select gate SSL and the p-well PWI.

[0037] The driving voltage GSSL drives the select gate SSL in part of the erase operation. The adjustment unit 404 generates the driving voltage GSSL based on the voltage of the p-well PWI in the erase operation. The switch 402 conducts the driving voltage GSSL from the adjustment unit 404 to the pass transistor 406 when the switch 402 is closed. The switch 403 conducts the constant voltage 0 V as the driving voltage GSSL when the switch 403 is closed. The pass transistor 406 is an n-channel metal-oxide-semiconductor field-effect transistor. The pass transistor 406 turns on and conducts the driving voltage GSSL to the select gate SSL when the bias voltage PASS_GATE rises to a high voltage (for example, 4 V). The adjustment unit 404 can adjust and reduce the driving voltage from PWI to GSSL so that the voltage of the select gate SSL does not rise too high in the erase operation.

[0038] The bias voltage PASS_GATE equal to 4 V is just an example. In another embodiment of the present invention, the bias voltage PASS_GATE may be replaced with another voltage other than 4 V.

[0039] A NAND flash memory includes a plurality of NAND strings. Each NAND string includes two select transistors. Each select transistor has a select gate. There may an independent circuit 400 for each select gate. Alternatively, a plurality of select gates in the NAND flash memory may share one or more elements of the circuit 400.

[0040] The present invention is not limited to NAND flash memories. In another embodiment, the circuit 400 may be applied to other non-volatile memories with similar structure and similar problem.

[0041] FIG. 5 is a schematic diagram showing a circuit 500 for adjusting select gate voltage for an erase operation of a non-volatile memory according to an embodiment of the present invention. In this embodiment, the adjustment unit 404 directly outputs the voltage of the p-well PWI as the driving voltage GSSL. In the erase operation, the voltage V.sub.ERS driving the p-well PWI is used directly to float the select gate SSL.

[0042] FIG. 6 is a timing diagram showing some voltage signals in the circuit 500 in FIG. 5 according to an embodiment of the present invention. The voltage signals include the voltage PASS_GATE biasing the pass transistor 406, the driving voltage GSSL, the voltage of the select gate SSL, and the voltage of the p-well PWI.

[0043] As FIG. 6 shows, before t0 the switch 402 is opened and the switch 403 is closed. Therefore, GSSL is biased at 0 V via the switch 403. The gate side of pass transistor 406 is turn on to 4 V at t0 and stuck at 4 V all the time until t3. At t1, an erase voltage V.sub.ERS (for example, 20 V) is applied to the p-well PWI. In addition, the switch 403 opens and the switch 402 closes at t1. Once the driving voltage GSSL, which begins following the voltage of the p-well PWI at t1, surpasses (4 V−V.sub.TN), the pass transistor 406 is cut off and the select gate SSL becomes floated. V.sub.TN is the threshold voltage of the pass transistor 406. The dotted portion of the voltage of the select gate SSL represents the floating state of the select gate SSL. At t2 the p-well PWI is discharged. The driving voltage GSSL and the voltage of the select gate SSL decrease accordingly. The pass transistor 406 is turned on when the driving voltage GSSL falls below (4 V−V.sub.TN). The final voltage (the highest voltage) of the select gate SSL is:

V.sub.SSL,final=(4 V−V.sub.TN)+[V.sub.ERS−(4 V−V.sub.TN)]×R, 0<R<1

[0044] R is the coupling-ratio of the capacitive coupling 408. R is determined by the process of the NAND flash memory.

[0045] The adjustment units 404 in the following embodiments reduce the voltage of the p-well PWI to generate the driving voltage GSSL, such as reducing the voltage of the p-well PWI by a voltage divider or by one or more diodes.

[0046] FIG. 7 is a schematic diagram showing a circuit 700 for adjusting select gate voltage for an erase operation of a non-volatile memory according to an embodiment of the present invention. In this embodiment, instead of outputting the voltage of the p-well PWI directly, the adjustment unit 404 includes a voltage divider 710 coupled between the switch 402 and the p-well PWI. For example, the voltage divider 710 may be a resistor divider. The voltage divider 710 receives the voltage of the p-well PWI and outputs a fraction of the voltage of the p-well PWI as the driving voltage GSSL to bias the select gate SSL in the erase operation.

[0047] FIG. 8 is a timing diagram showing some voltage signals in the circuit 700 in FIG. 7 according to an embodiment of the present invention. FIG. 8 is similar to FIG. 7. The select gate SSL is floated only after the output of the voltage divider 710 is larger than (4 V−V.sub.TN). The final voltage (the highest voltage) of the select gate SSL becomes:

V.sub.SSL,final=(4 V−V.sub.TN)+[V.sub.ERS−(4 V−V.sub.TN)/D]×R, 0<R<1, 0<D<1

[0048] R is the coupling-ratio of the capacitive coupling 408. D is the divide-ratio of the voltage divider 710. In this embodiment, the select gate SSL is floated later than the case without the voltage divider 710. The duration of this latency depends on the charging speed of the p-well PWI and the divide-ratio D. The coupling voltage from the p-well PWI to the select gate SSL is reduced and the final voltage of the select gate SSL during erase operation is lower.

[0049] The voltage divider 710 divides the voltage of the p-well PWI according to the divide-ratio D to generate the aforementioned fraction of the voltage of the p-well PWI. The divide-ratio D may be a static value built in the voltage divider 710. Alternatively, the divide-ratio D may be a dynamic value received by the voltage divider 710 as an input signal. In this way, the final voltage of the select gate SSL in the erase operation can be adjusted and optimized to optimize the endurance and the reliability of the non-volatile memory.

[0050] FIG. 9 is a schematic diagram showing a circuit 900 for adjusting select gate voltage for an erase operation of a non-volatile memory according to an embodiment of the present invention. In this embodiment, the adjustment unit 404 includes a diode 910 coupled between the p-well PWI and the switch 402. Since the voltage of the p-well PWI has to pass through the diode 910 to bias the select gate SSL during erase operation, the voltage drop on the diode 910 can reduce the voltage of the p-well PWI to reduce the voltage of the select gate SSL. The adjustment unit 404 further includes another diode 920 coupled between the p-well PWI and the switch 402 to discharge the driving voltage GSSL. Without the diode 920, the diode 910 would block the discharging of the driving voltage GSSL.

[0051] FIG. 10 is a timing diagram showing some voltage signals in the circuit 900 in FIG. 9 according to an embodiment of the present invention. FIG. 10 is similar to FIG. 6. The select gate SSL is floated when the voltage of the p-well PWI is larger than the driving voltage GSSL by the voltage drop V.sub.D on the diode 910 and the driving voltage GSSL reaches (4 V−V.sub.TN). Therefore, the coupling voltage between the p-well PWI and the select gate SSL can be reduced by V.sub.D further. The final voltage (the highest voltage) of the select gate SSL in erase operation becomes:

V.sub.SSL,final=(4 V−V.sub.TN)+[V.sub.ERS−(4 V−V.sub.TN)−V.sub.D]×R, 0<R<1

[0052] FIG. 11 is a schematic diagram showing a circuit 1100 for adjusting select gate voltage for an erase operation of a non-volatile memory according to an embodiment of the present invention. In this embodiment, instead of a single diode 910, the adjustment unit 404 includes a plurality of diodes 910 coupled in series between the p-well PWI and the switch 402 to reduce the voltage of the p-well PWI. The multiple diodes 910 can further reduce the bias voltage of the select gate SSL.

[0053] FIG. 12 is a timing diagram showing some voltage signals in the circuit 1100 in FIG. 11 according to an embodiment of the present invention. FIG. 12 is similar to FIG. 10. Due to the plurality of the diodes 910, the final voltage (the highest voltage) of the select gate SSL in erase operation becomes:

V.sub.SSL,final=(4 V−V.sub.TN)+[V.sub.ERS−(4 V−V.sub.TN)−N*V.sub.d]×R, 0<R<1

[0054] R is the coupling-ratio between the p-well PWI and the select gate SSL, while N is the number of the diodes 910 coupled in series.

[0055] In the previous embodiments, the switch 402 is coupled to the pass transistor 406, while the adjustment unit 404 is coupled between the switch 402 and the p-well PWI. In another embodiment of the present invention, the positions of the switch 402 and the adjustment unit 404 may be exchanged. The adjustment unit 404 may be coupled to the pass transistor 406, while the switch 402 may be coupled between the adjustment unit 404 and the p-well PWI.

[0056] In an embodiment of the present invention, a method for adjusting a select gate voltage for an erase operation of a non-volatile memory is provided. The steps of the method may be executed by the circuit 400 in the previous embodiments. The details of the steps of the method are already discussed in the previous embodiments.

[0057] In summary, the circuit provided by the present invention can adjust the coupling voltage of select gates to get the optimal voltage for select gates in erase operation, so that non-volatile memory devices can withstand more repeated program/erase cycles without degradation of reliability.

[0058] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.