An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core Timing Control (CTC) signals that are used to control voltages applied in the memory structure. In one aspect, information from which the CTC signals may be generated is pre-computed and stored. This pre-computation may be performed in a power on phase of the memory system. When a request to perform a memory operation is received, the stored information may be accessed and used to generate the CTC signals to control the memory operation. Thus, considerable time and/or power is saved. Note that this time savings occurs each time the memory operation is performed. Also, power is saved due to not having to repeatedly perform the computation.

Methods and apparatus are disclosed for managing the storage of static and dynamic neural network data within a non-volatile memory (NVM) die for use with deep neural networks (DNN). Some aspects relate to separate trim sets for separately configuring a static data NVM array for static input data and a dynamic data NVM array for dynamic synaptic weight data. For example, the static data NVM array may be configured via one trim set for data retention, whereas the dynamic data NVM array may be configured via another trim set for write performance. The trim sets may specify different configurations for error correction coding, write verification, and read threshold calibration, as well as different read/write voltage thresholds. In some examples, neural network regularization is provided within a DNN by setting trim parameters to encourage bit flips to avoid overfitting. Some examples relate to managing non-DNN data, such as stochastic gradient data.

Methods and apparatus are disclosed for managing the storage of static and dynamic neural network data within a non-volatile memory (NVM) die for use with deep neural networks (DNN). Some aspects relate to separate trim sets for separately configuring a static data NVM array for static input data and a dynamic data NVM array for dynamic synaptic weight data. For example, the static data NVM array may be configured via one trim set for data retention, whereas the dynamic data NVM array may be configured via another trim set for write performance. The trim sets may specify different configurations for error correction coding, write verification, and read threshold calibration, as well as different read/write voltage thresholds. In some examples, neural network regularization is provided within a DNN by setting trim parameters to encourage bit flips to avoid overfitting. Some examples relate to managing non-DNN data, such as stochastic gradient data.

Methods and apparatus are disclosed for managing the storage of dynamic neural network data within bit-addressable memory devices, such phase change memory (PCM) arrays or other storage class memory (SCM) arrays. In some examples, a storage controller determines an expected amount of change within data to be updated. If the amount is below a threshold, an In-place Write is performed using bit-addressable writes via individual SET and RESET pulses. Otherwise, a modify version of an In-place Write is performed where a SET pulse is applied to preset a portion of memory to a SET state so that individual bit-addressable writes then may be performed using only RESET pulses to encode the updated data. In other examples, a storage controller separately manages static and dynamic neural network data by storing the static data in a NAND-based memory array and instead storing the dynamic data in a SCM array.

A memory system includes a memory chip, one or more signal lines including a first signal line, and a controller. The controller is connected to the memory chip via the one or more signal lines. The controller is configured to transmit and receive signals via the first signal line in accordance with a first standard under which voltages of communicated signals transition in a first range and with a second standard under which voltages of communicated signals transition in a second range narrower than the first range. The controller is configured to transmit a command to the memory chip via the first signal line in accordance with the first standard, and based on a response to the command from the memory chip, enable communication in accordance with the second standard.

A semiconductor device and an operation method capable of operating with high reliability are provided. A voltage monitoring circuit (100) of the disclosure includes: a power-on detection part (110) configurated to detect whether a supply voltage (EXVDD) of an external power supply terminal has reached a power-on voltage level; a timer (120) configurated to measure a predetermined time when the power-on voltage level is detected; a through current generation part (130) configurated to generate a through current between the external power supply terminal and GND during a period when the timer (120) measures the predetermined time; and a power-off detection part (140) configurated to detect whether a drop of the supply voltage (EXVDD) has reached a power-off voltage level when the through current is generated.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.

A memory device that includes a memory array and a memory controller is introduced. The memory controller is configured to adjust a program strength of the program pulse according to the configurable ratio of the first bit value and the second bit value to generate an adjusted program pulse or to adjust a bias voltage pair according to the configurable ratio of the first bit value and the second bit value to generate an adjusted bias voltage pair. The memory controller is further configured to generate the random bit stream with the configurable ratio of the first bit value and the second bit value according to the data stored in the plurality of memory cells included in the memory array after applying the adjusted program pulse or according to the data stored in the plurality of memory cells after being biased by the adjusted bias voltage pair.

A program method includes applying a first voltage to a plurality of bit lines, applying a second voltage to a common source line (CSL), and performing a program loop by applying a program voltage and a verify voltage to each of a plurality of ground selection lines (GSLs) positioned between one bit line among the plurality of bit lines and the CSL. The program loop is performed on both a program completed cell in which a program is completed by applying the program voltage and a program target cell.

Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.