Adaptive read threshold voltage tracking techniques are provided that employ bit error rate estimation based on a non-linear syndrome weight mapping. An exemplary device comprises a controller configured to determine a bit error rate for at least one of a plurality of read threshold voltages in a memory using a non-linear mapping of a syndrome weight to the bit error rate for the at least one of the plurality of read threshold voltages.

An object is to shorten the time for rewriting data in memory cells. A memory module includes a first memory cell, a second memory cell, a selection transistor, and a wiring WBL1. The first memory cell includes a first memory node. The second memory cell includes a second memory node. One end of the first memory cell is electrically connected to the wiring WBL1 through the selection transistor. The other end of the first memory cell is electrically connected to one end of the second memory cell. The other end of the second memory cell is electrically connected to the wiring WBL1. When the selection transistor is on, data in the first memory node is rewritten by a signal supplied through the selection transistor to the wiring WBL1. When the selection transistor is off, data in the first memory node is rewritten by a signal supplied through the second memory node to the wiring WBL1.

The abstract of the disclosure was objected to because of informality (e.g. format, reference to figures, etc.). See MPEP § 608.01 (b). Please amend the abstract to recite: Non-volatile memory device may include at least an array of memory cells. The non-volatile memory cells may include associated decoding and sensing circuitry and a memory controller. Methods for checking the erasing phase of a non-volatile device may include performing a dynamic erase operation of at least a memory block and storing in a dummy row at least an internal block variable of the dynamic erase operation and/or a known pattern.

The abstract of the disclosure was objected to because of informality (e.g. format, reference to figures, etc.). See MPEP § 608.01 (b). Please amend the abstract to recite: Non-volatile memory device may include at least an array of memory cells. The non-volatile memory cells may include associated decoding and sensing circuitry and a memory controller. Methods for checking the erasing phase of a non-volatile device may include performing a dynamic erase operation of at least a memory block and storing in a dummy row at least an internal block variable of the dynamic erase operation and/or a known pattern.

Numerous embodiments are disclosed for accessing redundant non-volatile memory cells in place of one or more rows or columns containing one or more faulty non-volatile memory cells during a program, erase, read, or neural read operation in an analog neural memory system used in a deep learning artificial neural network.

A memory device including: a memory block including a word lines, word lines located in the middle of the word lines are used as dummy word lines, a control circuit establish word lines stacked on one side and other side of the dummy word lines into a first and second sub-blocks, respectively, performs an independent erase operation on one of the first and second sub-blocks in an erase operation period, and a control logic differently sets a level of a first transfer voltage for controlling transfer of an erase common voltage to the selected sub-block and the level of a second transfer voltage for controlling transfer of the erase common voltage to the unselected sub-block, applies an erase allowable voltage from the erase common voltage to a word line of the selected sub-block, and floats a word line of the unselected sub-block, in the erase operation period.

A value-voltage-distribution-intersection-based read disturb information determination system includes a storage device coupled to a global read temperature identification system. The storage device identifies a value voltage distribution intersection of first and second value voltage distributions for respective first and second values in a first row in a storage subsystem in the storage device, and determines a default value voltage reference shift between a default value voltage reference level associated with the first value and the second value and the value voltage distribution intersection. Based on the default value voltage reference shift, the storage device determines read disturb information for the first row in the storage subsystem in the storage device, and uses it to generate a read temperature for a second row in the storage subsystem in the storage device that it provides to the global read temperature identification system.

A value-voltage-distribution-intersection-based read disturb information determination system includes a storage device coupled to a global read temperature identification system. The storage device identifies a value voltage distribution intersection of first and second value voltage distributions for respective first and second values in a first row in a storage subsystem in the storage device, and determines a default value voltage reference shift between a default value voltage reference level associated with the first value and the second value and the value voltage distribution intersection. Based on the default value voltage reference shift, the storage device determines read disturb information for the first row in the storage subsystem in the storage device, and uses it to generate a read temperature for a second row in the storage subsystem in the storage device that it provides to the global read temperature identification system.

According to one embodiment, a memory system includes a semiconductor memory and a controller. The memory system is capable of executing a first operation and a second operation. In the first operation, the controller issues a first command sequence, the semiconductor memory applies a first voltage to a first word line and applies a second voltage to a second word line to read data from the first memory, and the read data is transmitted to the controller from the semiconductor memory. In the second operation, the controller issues a second command sequence, the semiconductor memory applies a third voltage to the first word line and applies a fourth voltage to the second word line, and data held in the memory cell array is left untransmitted to the controller.

The present invention provides a method for accessing a flash memory module is disclosed, wherein the flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of block, each block is implemented by a plurality of word lines, each word line corresponds to K pages, and each word line includes a plurality of memory cells supporting a plurality of states, and the method includes the steps of: receiving data from a host device; generating dummy data; and writing the data with the dummy data to a plurality of specific blocks, wherein for each of a portion of the word lines of the specific blocks, the dummy data is written into at least one of the K pages, and the data from the host device is written into the other page(s) of the K pages.