A system includes a memory device having multiple dice and a processing device operatively coupled to the memory device. The processing device is to perform operations, including receiving a memory operation to program a set of pages of data across at least a subset of the plurality of dice. The operations further include partitioning the set of pages into a set of partitions, programming the set of partitions to the plurality of dice, and storing, in a metadata table, at least one bit to indicate that the set of pages is partitioned.

A write masked latch bit cell of an SRAM includes a write mask circuit that is responsive to assertion of a first write mask signal to cause a value of a write data node to be a first value and is responsive to assertion of a second write mask signal to cause the value of the write data node to have a second value. A pass gate supplies the data on the write data node to an internal node of the bit cell responsive to write word line signals being asserted. A keeper circuit maintains the value of the first node independently of values of the write word line signals while the first write mask signal and the second write mask signal are deasserted.

A programming pulse is caused to be applied to a wordline associated with a memory cell of the memory sub-system. A program verify operation is caused to be performed on the memory cell to determine that a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sensing node associated with the memory cell. A bitline voltage matching the measured threshold voltage is caused to be applied to a bitline associated with the memory cell to reduce a rate of programming associated with the memory cell.

A nonvolatile memory device is provided. A nonvolatile memory device comprises a word line, a bit line, a memory cell array including a first memory cell at an intersection region between the word line and the bit line, a word line voltage generating circuitry configured to generate a program voltage, the program voltage to be provided to the word line, a row decoder circuitry configured to receive the program voltage from the word line voltage generating circuitry and configured to provide the program voltage to the word line, a verification circuitry configured to generate a verification signal in response to verifying a success or a failure of programming of the first memory cell, and a control circuitry configured to apply the program voltage to the first memory cell in response to the verification signal, and configured to cut off the program voltage in response to the verification signal.

For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.

A non-volatile storage system includes a control circuit connected to non-volatile memory cells provides for progressive writing of data. That is, existing data is overwritten by new data without performing a traditional erase operation that changes the threshold voltage of the memory cells back to the traditional or original erase state. In one example, new data is written on top of old data using shifted threshold voltage distributions. Some embodiments include writing MLC data over SLC data, using intermediate erase threshold voltage distributions and/or automatically detecting which threshold voltage distributions are currently being used to store data.

A memory device includes a memory cell array, a page buffer circuit, and a counting circuit. The page buffer circuit includes a first and second page buffer columns connected to the memory cell array. The first page buffer column includes a first page buffer unit and the second page buffer column includes a second page buffer unit in a first stage. The first page buffer unit performs a first sensing operation in response to a first sensing signal, and the second page buffer unit performs a second sensing operation in response to a second sensing signal. The counting circuit counts a first number of memory cells included in a first threshold voltage region from a result of the first sensing operation, and counts a second number of memory cells included in a second threshold voltage region from a result of the second sensing operation.

A memory system includes a nonvolatile memory, a controller configured to control the nonvolatile memory, a power supply circuit that is connected to the controller and configured to generate a power supply voltage for the nonvolatile memory and the controller from a voltage supplied from at least one external power supply, and a power storage device that is connected to the power supply circuit and configured to charge to a first energy from a charging voltage supplied by the power supply circuit, and an energy sharing pin that is connected to the power supply circuit and the power storage device, and is connectable to an external power storage device in an external memory system.

A method includes identifying a target plane in respective planes of a memory die in a non-volatile memory array and identifying, from blocks of non-volatile memory cells coupled to a common bit line in the target plane, at least one target block in the target plane. The method further includes performing an operation to disable at least one gate associated with the at least one target block to prevent access to the blocks of non-volatile memory cells coupled to the common bit line in the target plane.

Provided is a nonvolatile memory device. The nonvolatile memory device includes a memory cell array, a first voltage generator configured to generate a word line operating voltage for each word line of the memory cell array, a second voltage generator configured to generate a bit line operating voltage of the memory cell array, and a temperature unit configured to determine, from a temperature range table, a temperature range for a temperature code according to a real-time temperature of the memory cell array, and to adjust a power supply voltage of the first or second voltage generator based on a selection signal mapped to the determined temperature range.