A read disturb information determination system includes a storage device coupled to a global read temperature identification system. The storage device reads, from a first row in a storage subsystem in the storage device, data stored in bits that were previously identified as being susceptible to read disturb effects, and error correction information associated with the data. The storage device uses the error correction information to identify a number of the bits that store portions of the data with errors and, based on the number of bits that store portions of the data with errors, determines read disturb information for the first row in the storage subsystem in the storage device. The storage device then uses the read disturb information to generate a read temperature for a second row in the storage subsystem in the storage device, and provides the read temperature to the global read temperature identification system.

A value-voltage-distribution-intersection-based read disturb information determination system includes a storage device coupled to a global read temperature identification system. The storage device identifies a value voltage distribution intersection of first and second value voltage distributions for respective first and second values in a first row in a storage subsystem in the storage device, and determines a default value voltage reference shift between a default value voltage reference level associated with the first value and the second value and the value voltage distribution intersection. Based on the default value voltage reference shift, the storage device determines read disturb information for the first row in the storage subsystem in the storage device, and uses it to generate a read temperature for a second row in the storage subsystem in the storage device that it provides to the global read temperature identification system.

Apparatuses and techniques are described for detecting and isolating defective blocks of memory cells in a multi-plane operation such as program or erase. In one aspect, a program operation begins in a multi-plane mode, for one block in each plane. If fewer than all blocks complete programming by the time a trigger number of program loops have been performed, one or more unpassed blocks are programmed further, one at a time, in a single plane mode. If the one or more unpassed blocks do not complete programming when a maximum allowable number of program loops have been performed, they are marked as bad blocks and disabled from further operations. In another aspect, when a trigger number of program loops have been performed, one or more unpassed blocks are subject to a word line leakage detection operation.

According to one embodiment, a memory system includes a semiconductor memory and a controller. The memory system is capable of executing a first operation and a second operation. In the first operation, the controller issues a first command sequence, the semiconductor memory applies a first voltage to a first word line and applies a second voltage to a second word line to read data from the first memory, and the read data is transmitted to the controller from the semiconductor memory. In the second operation, the controller issues a second command sequence, the semiconductor memory applies a third voltage to the first word line and applies a fourth voltage to the second word line, and data held in the memory cell array is left untransmitted to the controller.

A memory device and a method of correcting error in a memory device is provided. The memory device controller includes a memory array, a tie-breaker array, a write controller, a verify circuit, and a controller. The memory array includes a plurality of memory cells. The tie-breaker array includes a plurality of tie-breaker rows. The write controller is configured to apply a programming voltage to the memory array. The verify circuit is configured to apply a verify voltage to verify whether the memory cells in the memory array are in an unambiguous state or not. The controller is configured to enable one or more tie-breaker rows in additions to the memory array to adjust an output of the memory array when the memory cells in the memory array are in an ambiguous state.

Systems, apparatuses, and methods related to a flip-on-precharge disable operation are described herein. In an example, a flip-on-precharge disable operation can include activating a set of memory cells in a memory device to perform a memory access. The memory device can include a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device. The flip-on-precharge disable operation can further include receiving signaling indicative of a command for a precharge operation on a set of the plurality of sets of memory cells. The signaling can include one or more bits that indicates whether to disable a randomly performed flip operation on the set of memory cells. The flip-on-precharge disable operation can include, in response to the one or more bits indicating to disable the flip operation, performing the precharge operation without randomly performing the flip operation on the set of memory cells.

A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.

A memory device can dynamically select a voltage step size for programming (i.e., charging) memory cells. The memory device can increase the voltage step size to reduce programming time or decrease the voltage step size to reduce errors. The memory device can identify device conditions, such as temperature or amount of use (e.g., a count of program/erase cycles). The memory device can increase the voltage step size when the device conditions are less likely to cause errors (e.g., in a middle temperature range or below a threshold number of program/erase cycles) or can decrease the voltage step size when the device conditions are more likely to cause errors (e.g., in a high or low temperature range or above a threshold number of program/erase cycles).

A storage device performs a read operation, based on a temperature measured in a program operation or an erase operation. The storage device includes: a memory device including a plurality of memory blocks, the memory device measuring a temperature in a program operation or an erase operation; and a memory controller for setting an area in which the measured temperature is to be stored in the memory device, and controlling a read operation to be performed in the memory device. When a read command for a selected page among a plurality of pages included in each of the plurality of memory blocks is received from the memory controller, the memory device determines a read voltage and a pass voltage based on a temperature corresponding to the selected page and performs a read operation on the selected page by using the read voltage and the pass voltage.

Exemplary methods, apparatuses, and systems include receiving read operations. The read operations are divided into a current set of a sequence of read operations and one or more other sets of sequences of read operations. An aggressor read operation is selected from the current set. A position in the sequence of read operations in the current set is determined such that the position that is preceded by at least a minimum number of read operations following a previous data integrity scan in a previous set of read operations. A data integrity scan is performed on a victim of the aggressor read operation at the determined position in the sequence of the current set of read operations.