A storage device performs a read operation by restoring an ON cell count (OCC) from a power loss protection (PLP) area of a nonvolatile memory. The nonvolatile memory includes a memory blocks, a buffer memory and a controller. The buffer memory stores a first ON cell count (OCC1) indicating a number of memory cells turned ON by a first read voltage and a second ON cell count (OCC2) indicating a number of memory cells turned ON by a second read voltage among the memory cells connected to a reference word line. The controller stores the OCC1 for each of the memory blocks in the PLP area when a sudden power off occurs in the storage device.

A reading method for a cell string using multiple pass voltages includes a pre-charging step and a reading step to read a selected word line cell WL[k]. The pre-charging step comprises applying a positive pass voltage (V.sub.pass1) to the selected word line (WL[k]), the upper word lines (Upper WL) of the selected word line (WL[k]), at least one the lower word lines adjacent to the selected word line (WL[k]); and applying a negative pass voltage (V.sub.pass2) to the remaining lower word lines (Lower WL) except for WL[k−1]. The reading step comprises applying sequentially a first voltage which is lower than a read voltage (V.sub.verify) and the read voltage (V.sub.verify) to the selected word line WL[k], applying a second voltage to a common source line CSL and the unselected word lines and sensing a current or a voltage of the selected word line WL[k], thereby reading information stored in the selected word line WL[k].

Read reference levels are calibrated by calibrating integration times. An integration time is the length of time for which the charge on a sense node is allowed to change while the memory cell is being sensed. Calibrating the integration time is much faster than calibrating the reference voltage itself. This is due, in part, to reducing the number of different reference voltages that need to be applied during calibration. Calibrating the integration time may use different test integration times for a given read reference voltage, thereby reducing the number of read reference voltages. Hence, calibrating the integration time(s) is very efficient timewise. Also, power consumption may be reduced.

A method, a memory chip controller of a flash memory device, and a flash memory device. The memory chip controller includes processing circuitry to receive data for a first page of N pages of data; and program cells of a memory location of the device to an nth threshold voltage level Ln, Ln corresponding to a program verify voltage level PVn, n being an integer from 0 to 2.sup.N−1, and Ln being one of 2.sup.N threshold voltage levels achievable using the N pages of data. Programming the cells includes: programming the cells based on the data for the first page while receiving data for subsequent pages of the N pages; and programming the cells based on the data for the subsequent pages, wherein programming the cells includes, for at least n=1, causing a respective dynamic start voltage (DSV) to be applied to the cells based on each respective page number p of the N pages for which data is received at the memory chip controller for the memory location to achieve PV1.

Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.

A memory device includes memory cells, word lines that are each connected to gates of a plurality of the memory cells, bit lines that are each connected to a plurality of the memory cells, and a control circuit configured to perform a determination operation on the memory cells. During the determination operation for a first memory cell among the memory cells, a first bit line connected to the first memory cell is charged using a bit line charge voltage, and the bit line charge voltage is adjusted based on a result of a first sensing operation that is performed on the first bit line. A second sensing operation is performed on the first bit line after the first sensing operation to determine whether a threshold voltage of the first memory cell is greater than a reference voltage.

A memory device capable of narrowing the threshold voltage distribution thereof includes word lines, bit lines, memory cells, a word line driver configured to apply voltage to a selected word line, a sense amplifier circuit configured to detect data of the memory cell, and a controller configured to control the word line driver and the sense amplifier. A write sequence includes a write operation in which write voltage is applied to the selected word line by the word line driver, and a verify operation in which, when a threshold voltage of the selected memory cell reaches a reference voltage, writing to the selected memory cell is completed. Based on second data that is written later than the first data to an adjacent memory cell adjacent to the selected memory cell, the controller changes the reference voltage used for completing the writing to the selected memory cell.

The memory device includes a memory block including, a voltage generator, a pass switch group connecting or blocking the global lines and the local lines to each other or from each other in response to a block selection voltage, a decoder, and a logic circuit configured to control the decoder and the voltage generator so that the local lines are floated after initializing a channel of the strings and a voltage of the global lines is lower than a voltage of the global lines when initializing the channel of the strings, when a program operation of selected memory cells included in a selected page of the memory block is completed, the channels of the strings are initialized and the local lines are floated.

Control logic in a memory device initiates a program operation on the memory device, the program operation comprising a program phase, a program recovery phase, a program verify phase, and a program verify recovery phase. The control logic further causes a negative voltage signal to be applied to a first plurality of word lines of a data bock of the memory device during the program verify recovery phase of the program operation, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation and one or more data word lines adjacent to the selected word line.

The present disclosure relates to an electronic device. A memory device having improved cache program operation performance according to the present technology includes a plurality of memory cells, each programmed in any one of first to n-th program state where n is a natural number greater than, a sensing latch configured to store data sensed from a bit line connected to a selected memory cell among the plurality of memory cells, and a plurality of data latches configured to temporarily store data to be stored in the selected memory cell.