A high-reliability one-time programmable memory adopting series high voltage partition, which relates to integrated circuit technology and comprises a first MOS tube, a second MOS tube and an anti-fuse element, wherein a gate end of the first MOS tube is connected to a second connecting line (WS), a first connecting end of the first MOS tube is connected to a gate end of the second MOS tube and a voltage limiting device, and a second connecting end of the first MOS tube is connected to a third connecting line (BL); a first connecting end of the second. MOS tube is connected to a fourth connecting line (BR), a second connecting end of the second MOS tube is connected to the third connecting line (BL), and a gate end of the second MOS tube is connected to the voltage limiting device and the second connecting end of the first MOS tube.

According to an embodiment, there is provided a semiconductor memory device comprising: a global bit line; a local bit line to which a plurality of cell transistors are connected; a switch connected to the local bit line; signal lines connected to the plurality of cell transistors; and a control circuit, wherein the control circuit selects a cell transistor to be selected by setting a potential of the signal line of the cell transistor to be selected to a first potential, changes a potential of the global bit line, changes a potential of the local bit line, and turns on the switch to connect the local bit line to the global bit line after changing the potential of the global bit line and the potential of the local bit line.

An anti-fuse device includes: a well region disposed in a semiconductor substrate; a gate electrode disposed on a gate insulating film on the semiconductor substrate; and a first well bias tap region disposed below the gate insulating film and the gate electrode in the well region, wherein the well bias tap region is doped with dopants of a same conductivity type as the well region.

In an example, a memory array may include a memory cell around at least a portion of a semiconductor. The memory cell may include a gate, a first dielectric stack to store a charge between a first portion of the gate and the semiconductor, and a second dielectric stack to store a charge between a second portion of the gate and the semiconductor, the second dielectric stack separate from the first dielectric stack.

In an example, a memory array may include a memory cell around at least a portion of a semiconductor. The memory cell may include a gate, a first dielectric stack to store a charge between a first portion of the gate and the semiconductor, and a second dielectric stack to store a charge between a second portion of the gate and the semiconductor, the second dielectric stack separate from the first dielectric stack.

A one-time programming cell includes a first metal oxide semiconductor (MOS) structure and a second transistor having a common gate electrode electrically connected to a word line. The first MOS structure has a first gate dielectric layer and the second MOS structure has a second gate dielectric layer. The second gate dielectric layer is thicker than the first gate dielectric layer. Source nodes of the first MOS structure and the second MOS structure are electrically connected, and a drain node of the second MOS structure is electrically connected to a bit line.

A method to program bitcells of a ROM array uses different programming cells for programming the bitcells with a first or second data item. A first bitcell is programmed by means of a selected programming cell, wherein the programming cell is selected in dependence on operating the memory array as a flipped or a non-flipped memory in multi-bank instance. All other bitcells located in the same column as the first bitcell and subsequent rows are programmed by selected programming cells, wherein the selection of the programming cells is dependent on operating the memory array as a flipped or a non-flipped memory in multi-bank instance and the programming state of the programming cells used for the previously programmed bitcells in the same column.

An anti-fuse device includes: a well region disposed in a semiconductor substrate; a gate electrode disposed on a gate insulating film on the semiconductor substrate; and a first well bias tap region disposed below the gate insulating film and the gate electrode in the well region, wherein the well bias tap region is doped with dopants of a same conductivity type as the well region.

A write voltage generation circuit includes: a power supply terminal that receives an external power supply voltage; a boosting circuit that boosts the external power supply voltage to generate a boosted voltage; and a selector that selects either one of the external power supply voltage and the boosted voltage, and outputs the selected voltage as the write voltage. The selector selects the external power supply voltage as the write voltage in a first part of a write period for writing data to a memory cell, and selects the boosted voltage as the write voltage in a latter part of the write period.

A semiconductor device includes a word line coupled to a mask ROM memory cell, a bit line pair coupled to the memory cell, a differential sense amplifier for amplifying the potential difference of the bit line pair, and a logic circuit for detecting whether the logic states of the bit line pair match or not. In this way, when there is a failure in the memory cell, it is possible to prevent the semiconductor device from passing the test as a result of the determination that the actual value is the same as the expected value in the test even if there is no potential difference in the bit line pair.