A test circuit includes first integration circuit configured to receive first test signal and integrate first test signal to output first integrated signal; second integration circuit configured to receive second test signal and integrate second test signal to output second integrated signal, where first test signal and second test signal are signals inverted with respect to each other, value of first integrated signal is product of duty cycle of first test signal and a voltage amplitude of power supply, and value of second integrated signal is product of duty cycle of second test signal and voltage amplitude of power supply; and comparison circuit connected to first and second integration circuits. The comparison circuit is configured to output high-level signal in response to first integrated signal being greater than second integrated signal, and output low-level signal in response to second integrated signal being greater than first integrated signal.

A memory device to determine a voltage optimized to read a group of memory cells by reading the group of memory cells at a plurality of test voltages, computing bit counts at the test voltages respectively, and computing count differences in the bit counts for pairs of adjacent voltages in the test voltages. When a smallest one in the count differences is found at a side of a distribution of the count differences according to voltage, the memory device is configured to determine a location of an optimized read voltage, based on a ratio between a first count difference and a second count difference, where the first count difference is the smallest in the count differences, and the second count difference is closest in voltage to the first count difference.

Disclosed herein are related to a system and a method of extending a lifetime of a memory cell. In one aspect, a memory controller applies a first pulse having a first amplitude to the memory cell to write input data to the memory cell. In one aspect, the memory controller applies a second pulse having a second amplitude larger than the first amplitude to the memory cell to extend a lifetime of the memory cell. The memory cell may include a resistive memory device or a phase change random access memory device. In one aspect, the memory controller applies the second pulse to the memory cell to repair the memory cell in response to determining that the memory cell has failed. In one aspect, the memory controller periodically applies the second pulse to the memory cell to extend the lifetime of the memory cell before the memory cell fails.

An integrated circuit die includes memory sectors, each memory sector including a memory array. The die includes a voltage regulator with a first transistor driven by an output voltage to thereby generate a gate voltage, the output voltage being generated based upon a difference between a constant current and a leakage current. A selection circuit selectively couples the gate voltage to a selected one of the plurality of memory sectors. A leakage detector circuit drives a second transistor with the output voltage to thereby generate a copy voltage based upon a difference between a variable current and a replica of the constant current, increases the variable current in response to the copy voltage being greater than the gate voltage, and asserts a leakage detection signal in response to the copy voltage being less than the gate voltage, the leakage detection signal indicating excess leakage within the memory array.

A storage device includes a memory device and a memory controller. The memory device stores a history read table including root bit information, read voltage information, and error bit information on each of a plurality of memory blocks, and performs a read operation of reading data stored in the plurality of memory blocks based on the history read table. When the read operation fails, a memory controller changes a level of a read voltage, and controls the memory device to perform a read retry operation of retrying the read operation by using the changed read voltage. When the read retry operation passes, the memory controller determines whether the history read table is to be updated by comparing the root bit information of the read retry operation with the root bit information of the history read table.

An apparatus comprises a plurality of memory cells; a plurality of sense circuits, a sense circuit comprising a sense node selectively coupled to a bitline coupled to a first cell of the plurality of memory cells; and a controller to transpose a value indicative of a voltage of the first cell to the sense node; isolate the sense node from the bitline; and calibrate a parameter for the sense circuit based on outputs of the sense circuit for each of a plurality of different applied values of the parameter.

A system includes a memory device having a plurality of groups of memory cells and a processing device communicatively coupled to the memory device. The processing device is be configured to read a first group of memory cells of the plurality to determine a calibrated read voltage associated with the group of memory cells. The processing device is further configured to determine, using the calibrated read voltage associated with the first group of memory cells, a bit error rate (BER) of a second group of memory cells of the plurality. Prior to causing the memory device to perform a copyback operation on the plurality of groups of memory cells, the processing device is further configured to determine whether to perform a subsequent read voltage calibration on at least the second group of the plurality based, at least partially, on a comparison between the determined BER and a threshold BER.

A read technique for both SLC (single level cell) and MLC (multi-level cell) cross-point memory can mitigate drift-related errors with minimal or no drift tracking. In one example, a read at a higher magnitude voltage is applied first, which causes the drift for cells in a lower threshold voltage state to be reset. In one example, the read at the first voltage can be a full float read to minimize disturb. A second read can then be performed at a lower voltage without the need to adjust the read voltage due to drift.

A memory controller receives a multi-plane read request and identifies a set of actual read offsets for a set of pages in the multi-plane read request. The memory controller calculates a common read offset using the set of actual read offsets. The memory controller calculates an offset difference for. Each page. Each offset difference reflects the difference between an actual read offset for that page and the common read offset. The memory controller compares a particular page's offset difference to an offset difference threshold. The memory controller categorizes, based on the comparing, a first subset of pages from the set of pages into a single plane group and a second subset of pages from the set of pages into a multi-plane group. The memory controller performs a multi-plane read on the multi-plane group.

Disclosed herein is a semiconductor device including a non-volatile memory unit. The non-volatile memory unit has a subject current path disposed in a semiconductor integrated circuit and a fuse element inserted in series on the subject current path, and changes output data according to a voltage between both ends of the fuse element when supply of a subject current to the subject current path is intended. A current supply part that switches the subject current between a plurality of stages is disposed in the non-volatile memory unit.