A semiconductor memory device includes a buffer die and a plurality of memory dies. Each of the memory dies includes a memory cell array, an error correction code (ECC) engine and a test circuit. The memory cell array includes a plurality of memory cell rows, each including a plurality of volatile memory cells. The test circuit, in a test mode, generates a test syndrome and an expected decoding status flag indicating error status of the test syndrome, receives test parity data generated by the ECC engine based on the test syndrome and a decoding status flag indicating error status of the test parity data, and determines whether the ECC engine has a defect based on comparison of the test syndrome and the test parity data and a comparison of the expected decoding status flag and the decoding status flag.

A data storage system can utilize one or more data storage devices that employ a solid-state non-volatile read destructive memory consisting of ferroelectric memory cells. A leveling strategy can be generated by a wear module connected to the memory with the leveling strategy prescribing a plurality of memory cell operating parameters associated with different amounts of cell wear. The wear module may monitor activity of a memory cell and detect an amount of wear in the memory cell as a result of the monitored activity, which can prompt changing a default set of operating parameters for the memory cell to a first stage of operating parameters, as prescribed by the leveling strategy, in response to the detected amount of wear.

A memory device includes a first comparison circuit suitable for comparing read data read from a plurality of memory cells with write data written in the memory cells and outputting a comparison result, a path selection circuit suitable for transferring selected data selected among the read data and test data as read path data based on the comparison result of the first comparison circuit, and an output data alignment circuit suitable for converting the read path data into serial data to output the serial data as output data.

The present invention relates to a testing method, a testing system, and a testing apparatus for a semiconductor chip. The method includes: acquiring a target chip; obtaining an abnormal chip after a test of read and write functions is performed separately on a preset number of memory cells in an edge region of the target chip; recording location information of individual memory cells with abnormal read and write functions on the abnormal chip; judging whether an abnormality of read and write functions of the abnormal chip is a block abnormality based on the location information; wherein the abnormal chip refers to the target chip including the memory cell with abnormal read and write functions.

There are provided a memory system and an operating method of the memory system. The memory system includes: a main controller for transmitting main data having N bits through a main channel, where N is a positive integer; memory devices for storing sub-data constituting the main data, and transmitting the sub-data through sub-channels; and a sub-controller for communicating with the main controller through the main channel, and communicating with the memory devices through the sub-channels. The sub-controller generates the sub-data each having n bits where n is a positive integer less than N, by dividing the main data, generates sub-data strobe clocks by decreasing a frequency of a main data strobe clock synchronized with the main data, and transmits/receives the sub-data to/from the memory devices in synchronization with the sub-data strobe clocks.

A memory device includes a plurality of data input pads and at least one test data input pad. The memory device also includes a plurality of data input circuits corresponding to a plurality of channels, respectively, the plurality of data input circuits suitable for transmitting respective data received through the data input pads to the corresponding channels. The memory device further includes a test control circuit suitable for selecting at least one data input circuit among the plurality of data input circuits based on test mode information and suitable for controlling the selected data input circuit to transmit set data to the corresponding channel, during a test operation.

In some examples, a circuit comprises a first polyfuse and a first diode having a first diode anode and a first diode cathode, where the first diode anode is coupled to the first polyfuse. The circuit comprises a second polyfuse coupled to the first polyfuse and a second diode having a second diode anode and a second diode cathode, where the second diode cathode is coupled to the second polyfuse. The circuit comprises a probe pad coupled to the first diode cathode and the second diode anode.

A failure bit count (FBC) circuit for memory array is provided. The memory array includes pages each having plural sectors and a redundancy column. The FBC circuit includes FBC units, in which each FBC unit is respectively coupled to each sector for providing a failure bit count current; a redundancy FBC unit coupled to the redundancy column and provides a redundancy current; a switch having a first end and a second end capable of being switched to couple to one of outputs of the FBC units to receive the failure bit count current from one of the FBC units; a comparator having a first input end that receives a reference current, and a second input end that receives a measurement current obtained by adding the failure measurement current and the redundancy current, and an output end outputting a judge signal to indicate a number of failure bits for each sector.

Provided herein may be a memory system and a method of operating the same. The memory system may include a memory device including a plurality of memory blocks, the memory device being configured to output voltage information indicating whether an unstable state of an input voltage has occurred, the input voltage being provided to the memory device from an external power source, and a memory controller configured to store a read count indicating a number of times that one or more read operations are performed on each of the plurality of memory blocks and to control the memory device to move data stored in a first memory block for which the read count exceeds a threshold count to a second memory block, and configured to adjust the threshold count based on the voltage information.

The invention introduces a method for verifying memory interface, performed by a processing unit, to include: driving a physical layer of a memory interface to pull-high or pull-low a signal voltage on each Input-Output (IO) pin thereof to a preset level according to a setting; obtaining a verification result corresponding to each IO pin from the memory interface; and storing each verification result in a static random access memory (SRAM), thereby enabling a testing host to obtain each verification result of the SRAM through a test interface. The testing host may examine each verification result to know whether any unexpected error has occurred in signals on the IO pins of the memory interface.