A failure bit count (FBC) circuit for memory array is provided. The memory array includes pages each having plural sectors and a redundancy column. The FBC circuit includes FBC units, in which each FBC unit is respectively coupled to each sector for providing a failure bit count current; a redundancy FBC unit coupled to the redundancy column and provides a redundancy current; a switch having a first end and a second end capable of being switched to couple to one of outputs of the FBC units to receive the failure bit count current from one of the FBC units; a comparator having a first input end that receives a reference current, and a second input end that receives a measurement current obtained by adding the failure measurement current and the redundancy current, and an output end outputting a judge signal to indicate a number of failure bits for each sector.

A semiconductor memory device includes a memory cell array, a bit-line switch, a block switch, and a column decoder. The memory cell array includes memory blocks coupled to at least one word-line and each of the memory blocks includes memory cells. The bit-line switch is connected between a first half local input/output (I/O) line of a first memory block and a second half local I/O line of the first memory block. The block switch is connected between the second half local I/O line of the first memory block and a first half local I/O line of a second memory block adjacent to the first memory block. The column decoder includes a repair circuit that controls connections by applying a first switching control signal to the bit-line switch and a second switching control signal to the block switch.

A location of at least one fail bit to be repaired in a memory block of a memory is extracted from at least one memory test on the memory block. An available repair resource in the memory for repairing the memory block is obtained. It is checked, using machine learning, whether the at least one fail bit is unrepairable, according to the location of the at least one fail bit, and the available repair resource. When the checking indicates that the at least one fail bit is not unrepairable, it is determined whether a Constraint Satisfaction Problem (CSP) containing a plurality of constraints is solvable. The constraints correspond to the location of the at least one fail bit in the memory block, and the available repair resource. In response to determining that the CSP is not solvable, the memory block is marked as unrepairable or the memory is rejected.

In a method of testing a nonvolatile memory device including a first semiconductor layer in which and a second semiconductor layer is formed prior to the first semiconductor layer, circuit elements including a page buffer circuit are provided in the second semiconductor layer, an on state of nonvolatile memory cells which are not connected to the page buffer circuit is mimicked by providing a conducting path between an internal node of a bit-line connection circuit connected between a sensing node and a bit-line node of the page buffer circuit and a voltage terminal to receive a first voltage, a sensing and latching operation with the on state being mimicked is performed in the page buffer circuit and a determination is made as to whether the page buffer circuit operates normally is made based on a result of the sensing and latching operation.

A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.

A memory controller includes, in one embodiment, a memory interface and a controller circuit. The memory interface is configured to interface with a memory interface configured to interface with a memory having a plurality of memory blocks. Each memory block has a plurality of strings. The controller circuit is configured to perform a string defect leakage check on one of the memory blocks during a first programming operation of the one memory block, determine whether the one memory block has one or more string to string shorts based on the string defect leakage check, and resolve the string to string shorts in response to determining that the one of the memory blocks has the string to string shorts.

A data storage system includes a storage medium including a plurality of columns of memory cells, a storage controller coupled to the storage medium, and data path circuitry including a data bus coupled to the storage controller, the data bus configured to receive a plurality of bytes of data to be written to the plurality of columns of memory cells; a block of data latches having a pitch equal to a first number of bit lines of the plurality of columns of memory cells; and column redundancy circuitry configured to pass the plurality of bytes of data to the block of data latches via the plurality of columns in accordance with a nonconsecutive mapping scheme. The nonconsecutive mapping scheme includes mapping each group of three bytes to two columns by splitting one byte of each group of three bytes into two nibbles.

Disclosed herein is an apparatus that includes a plurality of column planes each including a plurality of bit lines, an access control circuit configured to select one of the plurality of bit lines in each of the plurality of column planes based on a column address to read a plurality of data-bits, a data generating circuit configured to generate an expected-bit based at least in part on the data-bits, and an analyzing circuit configured to generate a fail-bit data indicating which one of the data-bits does not match the expected-bit when one of the data-bits does not match the expected-bit.

A static random-access memory and a fault detection circuit thereof are provided. The fault detection circuit includes: a bit line coupling circuit, coupled between a first bit line and a second bit line, wherein the bit line coupling circuit is adapted to use a bit line with a lower potential between the first bit line and the second bit line to couple a bit line with a higher potential between the first bit line and the second bit line to a floating low potential in response to performing the data write operation on the memory cell in a test mode by the write circuit; and a fault determining circuit, adapted to, in response to the memory cell being at the test mode, obtain and compare write data and read data corresponding to the write data, to determine whether the SRAM has a Data Retention Fault based on a comparison result.

A method for determining a repaired line and a repairing line in a memory includes the following: writing first preset data sets into respective lines in a normal region, and writing second preset data sets into respective lines in a redundancy region; repairing the lines in the normal region by using the lines in the redundancy region; reading data from the lines in the normal region after repairing; and determining a repaired line in the normal region and a repairing line in the redundancy region according to the data of the lines in the normal region, the data of the lines in the normal region after repairing, or the data of the lines in the redundancy region.