A memory test circuit comprising: a first latch circuit for receiving a first input address and an error indication signal to generate a first address; a first E-fuse group for receiving the first address to generate an output address; a second latch circuit for receiving the error indication signal; a second E-fuse group for generating an error indication signal according to an output of the second latch circuit which is generated according to the fault indication signal; and a comparison circuit for activating the second latch circuit according to a relation between the first address and a second input address and a state of the first latch circuit or the first E-fuse group.

Apparatuses and methods of sharing error correction memory on an interface chip are described. An example apparatus includes: at least one memory chip having a plurality of first memory cells and an interface chip coupled to the at least one memory chip and having a control circuit and a storage area. The control circuit detects one or more defective memory cells of the first memory cells of the at least one memory chip. The control circuit further stores first defective address information of the one or more defective memory cells of the first memory cells into the storage area. The interface chip responds to the first defective address information and an access request to access the storage area in place of the at least one memory chip when the access request has been provided with respect to the one or more defective memory cells of the first memory cells.

Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for repartitioning the stack of memory dies and storing the new partitions in a memory map. Repartitioning in selected configurations allows portions of memory to be removed from use without affecting the rest of the memory device. Additional devices, systems, and methods are disclosed.

Provided are a Fail Bit (FB) repair solution determination method and device, which are applied to a chip including multiple subdomains. The chip further includes Redundancy (RD) circuits, and the RD circuits are configured to repair FBs in the subdomains. The method includes that: after one or more available RD circuits are determined for a target FB presently to be repaired in a subdomain, a reliability value of each available RD circuit is acquired from an RD circuit reliability list, the RD circuit reliability list including reliability values of multiple RD circuits, and a repair solution for the target FB in the subdomain is determined according to the reliability value of the available RD circuit. The reliability value of the RD circuit is obtained by performing big data analysis on relationships between generated FBs and RD circuits where NFBs are located in the RD circuits.

A repair system and a repair method for a semiconductor structure, a storage medium, and an electronic device are provided. The semiconductor structure includes a main memory area and a redundant memory area. The repair system of the present disclosure includes a test circuit, a control circuit, and a repair circuit. The test circuit is configured to perform defect detection on the main memory area to determine a failed cell of the main memory area and position information of the failed cell. The control circuit is connected to the test circuit, and is configured to store the position information of the failed cell and generate a repair signal according to the position information. The repair circuit is connected to the control circuit, and is configured to receive the repair signal and perform a repair operation on the failed cell through the redundant memory area.

A control circuit, a memory system and a control method are provided. The control circuit is configured to control a plurality of memory cells of a memory array. The control circuit comprises a program controller. The program is configured to program a first electrical characteristic distribution and a second electrical characteristic distribution of the memory cells according to error tolerance of a first bit of a data type. A first overlapping area between the first electrical characteristic distribution and the second electrical characteristic distribution is smaller than a first predetermined value.

A system include multiple memory dice and a processing device coupled to the multiple memory dice. The processing device is to perform operations, including: reading temperature values from registers at multiple memory dice, wherein each temperature value is associated with a temperature at a respective die of the multiple memory dice; reading error-correcting code (ECC)-protected data from the multiple memory dice; determining whether an ECC check of the ECC-protected data results in detecting an error; in response to detecting the error from the ECC-protected data for a die of the multiple memory dice, performing a confirmation check that the error is a result of a defect in the die; and in response to the confirmation check confirming the die is defective, ignoring a temperature value from the die when determining whether to trigger a thermal-related operation.

A control circuit, a memory system and a control method are provided. The control circuit is configured to control a plurality of memory cells of a memory array. The control circuit comprises a program controller. The program is configured to program a first electrical characteristic distribution and a second electrical characteristic distribution of the memory cells according to error tolerance of a first bit of a data type. A first overlapping area between the first electrical characteristic distribution and the second electrical characteristic distribution is smaller than a first predetermined value.

An apparatus may include a memory array, a test circuit coupled to the memory array, a counter circuit coupled to the test circuit and an input/output (I/O) circuit coupled to the counter circuit. During a test operation, the test circuit may receive blocks of data from the memory array and compare the data to detect errors in the blocks of data. The counter circuit may increment a count value in response to detection of an error by the test circuit, and the I/O circuit may provide the count value to an output. The test circuit may also provide test comparison data based on the received blocks of data, and the I/O circuit may provide one of the count value and the test comparison data to the output.

The present embodiments provides a memory repair solution finding device and method which find a fault by testing a memory and find a repair solution in parallel and dynamically reconfigure the stored fault information to minimize a repair solution searching time with an optimal repair rate.