The purposes of the present invention are: to provide a layered semiconductor device capable of improving production yield; and to provide a method for producing said layered semiconductor device. This layered semiconductor device has, layered therein, a plurality of semiconductor chips, a reserve semiconductor chip which is used as a reserve for the semiconductor chips, and a control chip for controlling the operating states of the plurality of semiconductor chips and the operating state of the reserve semiconductor chip. In such a configuration, the semiconductor chips and the reserve semiconductor chip include contactless communication units and operating switches. The semiconductor chips and the reserve semiconductor chip are capable of contactlessly communicating with another of the semiconductor chips via the contactless communication units. The control chip controls the operating states of the semiconductor chips by switching the operating switches of the semiconductor chips, and controls the operating state of the reserve semiconductor chip by switching the operating switch of the reserve semiconductor chip.

A memory circuit and a testing method thereof are provided. The memory circuit includes multiple stage non-volatile memory (NVM) devices. An Nth stage NVM device includes a logic memory circuit, an NVM element, a write circuit and a read circuit. The logic memory circuit receives external data via a data input terminal in a normal mode and receives test data via a test input terminal in a test mode. The write circuit writes the test data or the external data to the NVM element during a writing period. The read circuit transmits stored data stored in the NVM element to an output terminal of the logic memory circuit during a reading period.

An apparatus may include a memory array, a test circuit coupled to the memory array, a counter circuit coupled to the test circuit and an input/output (I/O) circuit coupled to the counter circuit. During a test operation, the test circuit may receive blocks of data from the memory array and compare the data to detect errors in the blocks of data. The counter circuit may increment a count value in response to detection of an error by the test circuit, and the I/O circuit may provide the count value to an output. The test circuit may also provide test comparison data based on the received blocks of data, and the I/O circuit may provide one of the count value and the test comparison data to the output.

A method of detecting faults in a register bank is disclosed. The register bank includes at least one chain of registers. The method comprises sequentially shifting parameters stored in each register of the chain to an output node of the chain and inverting each parameter and feeding each parameter back to an input node of that chain, and sequentially shifting the inverted parameters through the chain until all the non-inverted parameters have been output at the output node. A first checksum of the parameters output at the output node is calculated. The inverted parameters in each register of the chain are sequentially shifted to the output node of the chain. A second checksum of the inverted parameters output at the output node is calculated, and the first and second checksums are compared.

A memory test system may include: a data storage device including a nonvolatile memory device, and a controller configured to control an operation of the nonvolatile memory device; and a test device configured to: request a test to the data storage device; request, to the data storage device, an output of a variable to be generated through driving of a firmware for performing the test, while the test is performed in the data storage device; and determine whether the firmware is normally driven based on the variable outputted from the data storage device.

The purposes of the present invention are: to provide a layered semiconductor device capable of improving production yield; and to provide a method for producing said layered semiconductor device. This layered semiconductor device has, layered therein, a plurality of semiconductor chips, a reserve semiconductor chip which is used as a reserve for the semiconductor chips, and a control chip for controlling the operating states of the plurality of semiconductor chips and the operating state of the reserve semiconductor chip. In such a configuration, the semiconductor chips and the reserve semiconductor chip include contactless communication units and operating switches. The semiconductor chips and the reserve semiconductor chip are capable of contactlessly communicating with another of the semiconductor chips via the contactless communication units. The control chip controls the operating states of the semiconductor chips by switching the operating switches of the semiconductor chips, and controls the operating state of the reserve semiconductor chip by switching the operating switch of the reserve semiconductor chip.

According to one embodiment, there is provided a semiconductor device including a memory, an interface circuit, and a built-in self-test circuit. The memory includes a plurality of memory cells. The interface circuit is connected to the memory cell. The built-in self-test circuit is connected to the interface circuit and is accessible to the memory via the interface circuit. The built-in self-test circuit includes a test circuit and an analysis circuit. The analysis circuit is arranged on an output side of the test circuit and has a bit counter and a holding circuit.

In one example implementation according to aspects of the present disclosure, a system is provided that includes a host processing system and a memory device communicatively coupled to the host processing system. The memory device includes a memory device controller, a volatile memory module, and a non-volatile memory module. The memory device controller performs a method including writing a data pattern to the non-volatile memory module, reading the data pattern from the non-volatile memory module, comparing the data pattern from the non-volatile memory module to an expected data pattern, and, based at least in part on determining that the data pattern from the non-volatile memory module matches the expected data pattern, loading system data stored in the volatile memory module to the non-volatile memory module when the host processing system experiences a power loss.

Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for repartitioning the stack of memory dies and storing the new partitions in a memory map. Repartitioning in selected configurations allows portions of memory to be removed from use without affecting the rest of the memory device. Additional devices, systems, and methods are disclosed.

A test mode control circuit relating to a technology for controlling a vendor specific test mode is disclosed. The test mode control circuit includes a signal generation circuit configured to generate a plurality of set signals and a plurality of reset signals in response to a plurality of code signals and a predetermined mode register signal; and a plurality of serially-connected latch circuits configured to selectively operate in response to the plurality of set signals and the plurality of reset signals so as to control an entry signal of an output terminal.