A semiconductor memory device includes a plurality of planes defined in a plurality of chip regions; and a rescue circuit configured to disable a failed plane and enable a normal plane from among the plurality of planes, wherein the semiconductor memory device operates with only normal planes that are enabled.

A semiconductor memory device includes a plurality of planes defined in a plurality of chip regions; and a rescue circuit configured to disable a failed plane and enable a normal plane from among the plurality of planes, wherein the semiconductor memory device operates with only normal planes that are enabled.

Memory devices may have an array of elements in two or more dimensions. The memory devices use multiple access lines arranged in a grid to access the memory devices. Memory cells located at intersections of the access lines in the grid. Drivers are used for each access line and configured to transmit a corresponding signal to respective memory cells of the plurality of memory cells via a corresponding access line. The memory devices may use an address scrambler to determine a bit error rate for accessing memory cells and remap an address of a particular memory cell to have a bit error rate below a threshold. In this way, the address scrambler may distribute the bit error rates of multiple accesses of the array.

Memory devices may have an array of elements in two or more dimensions. The memory devices use multiple access lines arranged in a grid to access the memory devices. Memory cells located at intersections of the access lines in the grid. Drivers are used for each access line and configured to transmit a corresponding signal to respective memory cells of the plurality of memory cells via a corresponding access line. The memory devices may use an address scrambler to determine a bit error rate for accessing memory cells and remap an address of a particular memory cell to have a bit error rate below a threshold. In this way, the address scrambler may distribute the bit error rates of multiple accesses of the array.

Various aspects include methods and devices for implementing the methods for error checking a memory system. Aspects may include receiving, from a row buffer of a memory, access data corresponding to a column address of a memory access, in which the row buffer has data of an activation unit of the memory corresponding to a row address of the memory access, determining multiple error correction codes (ECCs) for the access data using the column address, and checking the access data for an error utilizing at least one of the multiple ECCs. In some aspects, the multiple ECCs may include a first ECC having data from an access unit of the memory corresponding with the column address, and at least one second ECC having data from the access unit and data from the activation unit other than from the access unit.

A word line control method, a word line control circuit device, and a semiconductor memory are provided. The method includes: acquiring a row address input signal; acquiring a test mode signal; performing logical and decoding operations on the row address input signal and the test mode signal to generate a row address control signal, wherein the row address control signal includes at least two valid activation signals; and simultaneously activating at least two non-adjacent word lines based on the at least two valid activation signals. The row address control signal obtained allows simultaneous activation of at least two non-adjacent word lines. Since none of any two non-adjacent word lines share a common contact area, a test will not be affected by the disconnection of a contact area or the presence of high impedance, thus improving test accuracy.

A word line control method, a word line control circuit device, and a semiconductor memory are provided. The method includes: acquiring a row address input signal; acquiring a test mode signal; performing logical and decoding operations on the row address input signal and the test mode signal to generate a row address control signal, wherein the row address control signal includes at least two valid activation signals; and simultaneously activating at least two non-adjacent word lines based on the at least two valid activation signals. The row address control signal obtained allows simultaneous activation of at least two non-adjacent word lines. Since none of any two non-adjacent word lines share a common contact area, a test will not be affected by the disconnection of a contact area or the presence of high impedance, thus improving test accuracy.

Methods, apparatuses and systems related to managing repair assets are described. An apparatus stores a repair segment locator and a repair address for each defect repair. The apparatus may be configured to selectively apply a repair asset to one of multiple sections according to the repair segment locator.

Methods, apparatuses and systems related to managing repair assets are described. An apparatus stores a repair segment locator and a repair address for each defect repair. The apparatus may be configured to selectively apply a repair asset to one of multiple sections according to the repair segment locator.

Disclosed herein is an apparatus that includes a plurality of memory sections each including a plurality of word lines, a predecoder circuit configured to generate predecoded section address signals to select one of the plurality of memory sections and predecoded word line address signals to select one of the word lines included in a selected one of the plurality of memory sections based on a row address, and a section address control circuit configured to retain the predecoded section address signals regardless of an update of the row address in a test operation mode.