The present disclosure includes apparatuses, methods, and systems for programming codewords for error correction operations to memory. An embodiment includes a memory having a plurality of groups of memory cells, wherein each respective one of the plurality of groups includes a plurality of sub-groups of memory cells, and circuitry configured to program a portion of a codeword for an error correction operation to one of the plurality of groups of memory cells by determining an address in that group of memory cells by performing an XOR operation on an address of one of the plurality of sub-groups of that group of memory cells, and programming the portion of the codeword to the determined address.

The present disclosure includes apparatuses, methods, and systems for programming codewords for error correction operations to memory. An embodiment includes a memory having a plurality of groups of memory cells, wherein each respective one of the plurality of groups includes a plurality of sub-groups of memory cells, and circuitry configured to program a portion of a codeword for an error correction operation to one of the plurality of groups of memory cells by determining an address in that group of memory cells by performing an XOR operation on an address of one of the plurality of sub-groups of that group of memory cells, and programming the portion of the codeword to the determined address.

A memory controller receives a multi-plane read request and identifies a set of actual read offsets for a set of pages in the multi-plane read request. The memory controller calculates a common read offset using the set of actual read offsets. The memory controller calculates an offset difference for. Each page. Each offset difference reflects the difference between an actual read offset for that page and the common read offset. The memory controller compares a particular page's offset difference to an offset difference threshold. The memory controller categorizes, based on the comparing, a first subset of pages from the set of pages into a single plane group and a second subset of pages from the set of pages into a multi-plane group. The memory controller performs a multi-plane read on the multi-plane group.

A memory controller receives a multi-plane read request and identifies a set of actual read offsets for a set of pages in the multi-plane read request. The memory controller calculates a common read offset using the set of actual read offsets. The memory controller calculates an offset difference for. Each page. Each offset difference reflects the difference between an actual read offset for that page and the common read offset. The memory controller compares a particular page's offset difference to an offset difference threshold. The memory controller categorizes, based on the comparing, a first subset of pages from the set of pages into a single plane group and a second subset of pages from the set of pages into a multi-plane group. The memory controller performs a multi-plane read on the multi-plane group.

A memory device in accordance with a described method of operation includes a read only memory (ROM) address controller and a suspend signal generator. The ROM address controller is configured to sequentially output a plurality of operation ROM addresses at which ROM codes to be executed in response to an operation command are stored, and to suspend output of the plurality of operation ROM addresses in response to a suspend signal. The suspend signal generator is configured to generate the suspend signal that is activated during a preset period depending on whether a suspend ROM address is identical to an operation ROM address, among the plurality of operation ROM addresses, currently being output. The suspend ROM address is an address at which a ROM code, execution of which is to be suspended, among the ROM codes, is stored.

A memory device in accordance with a described method of operation includes a read only memory (ROM) address controller and a suspend signal generator. The ROM address controller is configured to sequentially output a plurality of operation ROM addresses at which ROM codes to be executed in response to an operation command are stored, and to suspend output of the plurality of operation ROM addresses in response to a suspend signal. The suspend signal generator is configured to generate the suspend signal that is activated during a preset period depending on whether a suspend ROM address is identical to an operation ROM address, among the plurality of operation ROM addresses, currently being output. The suspend ROM address is an address at which a ROM code, execution of which is to be suspended, among the ROM codes, is stored.

The disclosure relates to a method and system for memory testing to detect memory errors during operation of a memory module. Example embodiments include a method of detecting an error in a memory module (101), the method comprising the sequential steps of: i) receiving (302) a request from a processor executing an application for a read or write operation at a location of the memory module (101) identified by an address; ii) outputting data (304) from, or writing to, the location of the memory module (101); iii) generating (306) by an error detection module (102) a further read request for the location of the memory module (101) identified by the address; iv) receiving (307) at the error detection module (102) an error correction code from the memory module (101) for the location identified by the address; and vi) providing (311) by the error detection module (102) an alert output for the address if the error correction code indicates an error.

The disclosure relates to a method and system for memory testing to detect memory errors during operation of a memory module. Example embodiments include a method of detecting an error in a memory module (101), the method comprising the sequential steps of: i) receiving (302) a request from a processor executing an application for a read or write operation at a location of the memory module (101) identified by an address; ii) outputting data (304) from, or writing to, the location of the memory module (101); iii) generating (306) by an error detection module (102) a further read request for the location of the memory module (101) identified by the address; iv) receiving (307) at the error detection module (102) an error correction code from the memory module (101) for the location identified by the address; and vi) providing (311) by the error detection module (102) an alert output for the address if the error correction code indicates an error.

The embodiments provide a method for reading and writing and a memory device. The method includes: applying a read command to the memory device, the read command pointing to address information; reading data to be read out from a memory cell corresponding to the address information pointed to by the read command; storing the address information pointed to by the read command into a memory bit of a preset memory space if an error occurs in the data to be read out, wherein the preset memory space is provided with a plurality of the memory bits, each of the plurality of memory bits being associated with a spare memory cell; and backing up the address information stored in the preset memory space into a non-volatile memory cell according to a preset rule.

The embodiments provide a method for reading and writing and a memory device. The method includes: applying a read command to the memory device, the read command pointing to address information; reading data to be read out from a memory cell corresponding to the address information pointed to by the read command; storing the address information pointed to by the read command into a memory bit of a preset memory space if an error occurs in the data to be read out, wherein the preset memory space is provided with a plurality of the memory bits, each of the plurality of memory bits being associated with a spare memory cell; and backing up the address information stored in the preset memory space into a non-volatile memory cell according to a preset rule.