The present application relates to the technical field of integrated circuits, and in particular, to a memory test method and a memory test apparatus. The memory test method includes: providing a to-be-tested memory, where the to-be-tested memory includes a plurality of memory cells; alternately writing a first write value and a second write value into a memory cell of the memory cells at a preset frequency; writing a test write value into the memory cell; judging whether a data read from the memory cell is the test write value, and determining that a capacitance-frequency characteristic of the memory cell is abnormal if the data is not the test write value. According to the present application, the capacitance-frequency characteristic of the to-be-tested memory is accurately tested, to improve the field of memory products.

A semiconductor system including: an operation period adjusting circuit configured to generate operation information for adjusting an operation period, when an input count of an active command during a test mode period is equal to or more than a preset count; and a command generation circuit configured to adjust the input count of the active command applied to a semiconductor device during a preset period, by adjusting the operation period on the basis of the operation information.

A semiconductor system including: an operation period adjusting circuit configured to generate operation information for adjusting an operation period, when an input count of an active command during a test mode period is equal to or more than a preset count; and a command generation circuit configured to adjust the input count of the active command applied to a semiconductor device during a preset period, by adjusting the operation period on the basis of the operation information.

A system for outputting test data from cores to one communication interface. The system includes shared memories corresponding to the cores. Each shared memory includes a ring buffer and an array of slots. Each core generates a diagnostic message, and stores the generated diagnostic message in a select memory region of the ring buffer corresponding to a first empty slot of the array of slots. A selected core finds a first diagnostic message among diagnostic messages stored in the shared memories, and outputs the first diagnostic message to a personal computer through the communication interface.

A system for outputting test data from cores to one communication interface. The system includes shared memories corresponding to the cores. Each shared memory includes a ring buffer and an array of slots. Each core generates a diagnostic message, and stores the generated diagnostic message in a select memory region of the ring buffer corresponding to a first empty slot of the array of slots. A selected core finds a first diagnostic message among diagnostic messages stored in the shared memories, and outputs the first diagnostic message to a personal computer through the communication interface.

The present disclosure relates to a method for generating a pattern of a memory, a computer-readable storage medium and a computer device, the method for generating a pattern of a memory includes: presetting mapping relationships between a physical address and a row, a column and a bank, and determining bits of the physical address corresponding to the row, the column and the bank; taking a preset number of values as setting data, the preset number being the same as a number of signal address lines in the memory; obtaining a command truth value table, which is used to define relationships between bits of the physical address and commands; determining values of the row, the column and the bank based on the command truth value table and the setting data; generating the pattern based on the values of the row, the column and the bank and the mapping relationships.

The present disclosure relates to a method for generating a pattern of a memory, a computer-readable storage medium and a computer device, the method for generating a pattern of a memory includes: presetting mapping relationships between a physical address and a row, a column and a bank, and determining bits of the physical address corresponding to the row, the column and the bank; taking a preset number of values as setting data, the preset number being the same as a number of signal address lines in the memory; obtaining a command truth value table, which is used to define relationships between bits of the physical address and commands; determining values of the row, the column and the bank based on the command truth value table and the setting data; generating the pattern based on the values of the row, the column and the bank and the mapping relationships.

An apparatus including a test validation circuit and associated systems and methods are disclosed herein. The apparatus may include a self-test circuit configured to implement at least a portion of a self-test process that determines operating conditions of the apparatus. The test validation circuit may be configured to generate a flag based on comparing (1) an input stream or a portion thereof associated with the self-test to (2) test data associated with the self-test. The flag may represent a validity associated with the implementation of the self-test process or the portion thereof.

An apparatus including a test validation circuit and associated systems and methods are disclosed herein. The apparatus may include a self-test circuit configured to implement at least a portion of a self-test process that determines operating conditions of the apparatus. The test validation circuit may be configured to generate a flag based on comparing (1) an input stream or a portion thereof associated with the self-test to (2) test data associated with the self-test. The flag may represent a validity associated with the implementation of the self-test process or the portion thereof.

A digital system includes a non-volatile calculating register having a set of latches configured to perform a calculation. A set of non-volatile storage cells is coupled to the set of latches. Access detection logic is coupled to the calculating register and is operable to initiate a calculation of a next value by the calculating register each time the calculating register is accessed by an accessing module. The access detection logic is operable to cause the next value to be stored in the set of non-volatile storage cells at the completion of the calculation as an atomic transaction. After a power loss or other restore event, the contents of the calculating register may be restored from the non-volatile storage cells.