A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes: line type bits configured to store an indication that a corresponding cache line of the second sub-cache is configured to store write-miss data, and an eviction controller configured to evict a cache line of the second sub-cache storing write-miss data based on an indication that the cache line has been fully written.

A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller includes an error correction code (ECC) circuit. The ECC circuit is configured to determine data rows of first write data that are not all zeros and store the determined data rows in buffer rows of a buffer along with corresponding row indexes. The memory controller is configured to write second data based on the buffer to the memory device.

A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller includes an error correction code (ECC) circuit. The ECC circuit is configured to determine data rows of first write data that are not all zeros and store the determined data rows in buffer rows of a buffer along with corresponding row indexes. The memory controller is configured to write second data based on the buffer to the memory device.

A memory sub-system configured to: measure a plurality of sets of signal and noise characteristics of a group of memory cells in a memory device; determine a plurality of optimized read voltages of the group of memory cells from the plurality of sets of signal and noise characteristics respectively; generate features from the plurality of sets of signal and noise characteristics, including at least one compound feature generated from the plurality of sets of signal and noise characteristics; generate, using the features, a classification of a bit error rate of data retrievable from the group of memory cells; and control an operation to read the group of memory cells based on the classification.

A memory controller includes a memory channel controller adapted to receive memory access requests and dispatch associated commands addressable in a system memory address space to a non-volatile storage class memory (SCM) module. The non-volatile error reporting circuit identifies error conditions associated with the non-volatile SCM module and maps the error conditions from a first number of possible error conditions associated with the non-volatile SCM module to a second, smaller number of virtual error types for reporting to an error monitoring module of a host operating system, the mapping based at least on a classification that the error condition will or will not have a deleterious effect on an executable process running on the host operating system.

A memory device to program a group of memory cells to store multiple bits per memory cell. Each bit per memory cell in the group from a page. After determining a plurality of read voltages of the group of memory cells, the memory device can read the multiple pages of the group using the plurality of read voltages. For each respective page in the multiple pages, the memory device can determine a count of first memory cells in the respective page that have threshold voltages higher than a highest read voltage, among the plurality of read voltages, used to read the respective page. The count of the first memory cells can be compared with a predetermined range of a fraction of memory cells in the respective page to evaluate the plurality of read voltages (e.g., whether any of the read voltages is in a wrong voltage range).

A memory device to program a group of memory cells to store multiple bits per memory cell. Each bit per memory cell in the group from a page. After determining a plurality of read voltages of the group of memory cells, the memory device can read the multiple pages of the group using the plurality of read voltages. For each respective page in the multiple pages, the memory device can determine a count of first memory cells in the respective page that have threshold voltages higher than a highest read voltage, among the plurality of read voltages, used to read the respective page. The count of the first memory cells can be compared with a predetermined range of a fraction of memory cells in the respective page to evaluate the plurality of read voltages (e.g., whether any of the read voltages is in a wrong voltage range).

According to one embodiment, a memory device includes a first nonvolatile memory die, a second nonvolatile memory die, a controller, and a first temperature sensor and a second temperature sensor incorporated respectively in the first nonvolatile memory die and the second nonvolatile memory die. The controller reads temperatures measured by the first and second temperature sensors, from the first and second nonvolatile memory dies. When at least one of the temperatures read from the first and second nonvolatile memory dies is equal to or higher than a threshold temperature, the controller reduces a frequency of issue of commands to the first and second nonvolatile memory dies or a seed of access to the first and second nonvolatile memory dies.

A repair circuit includes: a plurality of redundant memory cells, each redundant memory cell being configured with a state signal; and a repair module connected to the plurality of redundant memory cells and configured to determine target memory cells from the redundant memory cells based on the state signals and repair defective memory cells through the target memory cells. The target memory cells are in one-to-one correspondence to the defective memory cells. The repair module can repair, at each of multiple repair stages, different defective memory cells, the plurality of redundant memory cells being shared at the multiple repair stages.

A system includes a memory array of sub-blocks, each sub-block including groups of memory cells, and a processing device. The processing device causes a first wordline to be programmed through the sub-blocks with a mask by causing to be programmed, to a first voltage level: a first group of memory cells of a first sub-block; and a second group of memory cells of a second sub-block. The processing device further scans a second wordline that has been programmed and is coupled to the first wordline, scanning includes: causing a custom wordline voltage to be applied to the second wordline, the custom wordline voltage to select groups of memory cells corresponding to those of the first wordline programmed to the first voltage level; concurrently reading data from the selected groups of memory cells of the second wordline; and performing, using the data, an error check of the second wordline.