A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.

A neuromorphic device includes a memory cell array including first resistive memory cells connected to word lines, bit lines and source lines, second resistive memory cells connected to the word lines, at least one redundancy bit line and at least one redundancy source line, third resistive memory cells connected to at least one redundancy word line, the bit lines and the source lines. The memory cell array stores data corresponding to a weight of a neural network in the first resistive memory cells, and is configured to generate a plurality of read currents based on input signals and the data. The neuromorphic device further includes an analog to digital converter (ADC) circuit configured to convert the plurality of read currents into a plurality of digital signals.

An apparatus includes a device programmer, coupled to a plurality of semiconductor fuses disposed on a die, configured to program the plurality of semiconductor fuses with compressed configuration data for a plurality of cores disposed separately on the die. The device programmer has a virtual fuse array and a compressor. The virtual fuse array is configured to store the configuration data for the plurality of cores. The configuration data includes a plurality of data types. The compressor is coupled to the virtual fuse array and is configured to read the virtual fuse array, and is configured to compress the configuration data by employing a plurality of compression algorithms to generate the compressed configuration data, where the plurality of compression algorithms correspond to the plurality of data types.

A dynamic random access memory (DRAM) comprises a plurality of primary data storage elements, a plurality of redundant data storage elements, and circuitry to receive a first register setting command and initiate a repair mode in the DRAM in response to the first register setting command. The circuitry is further to receive an activation command, repair a malfunctioning row address in the DRAM, receive a precharge command, receive a second register setting command, terminate the repair mode in the DRAM in response to the second register setting command, receive a memory access request for data stored at the malfunctioning row address, and redirect the memory access request to a corresponding row address in the plurality of redundant data storage elements.

Systems and devices for signal redundancy in stacked chip architectures can include an integrated circuit that incorporates a voting circuit. The voting circuit can be configured to receive multiple redundant copies of a signal input and remedy faults in a transmission pathway of the signal input by producing a signal output that reflects a majority among received versions of the signal input.

A memory device includes: a memory cell region including normal cells coupled to normal column selection lines, and row-hammer cells and redundancy cells respectively coupled to redundancy column selection lines; a repair control circuit configured to provide repair addresses and row-hammer flag signals, corresponding to repair information, according to a row address; and a column control circuit configured to activate at least one of the redundancy column selection lines according to the row-hammer flag signals or a comparison result of a column address and the repair addresses.

A memory device includes: a memory cell region including normal cells coupled to normal column selection lines, and row-hammer cells and redundancy cells respectively coupled to redundancy column selection lines; a repair control circuit configured to provide repair addresses and row-hammer flag signals, corresponding to repair information, according to a row address; and a column control circuit configured to activate at least one of the redundancy column selection lines according to the row-hammer flag signals or a comparison result of a column address and the repair addresses.