A system includes a processor and a memory set coupled to the processor. The system also includes a repair circuit coupled to the memory set. The repair circuit includes a first repair circuit and a second repair circuit. The repair circuit also includes a test controller configured to select between the first repair circuit and the second repair circuit to perform an in-field self-repair of the memory set.

Systems and methods for repairing a memory. A method includes performing a repair analysis of the embedded memories to produce repair information. The method includes storing the repair information in the registers, where the registers are organized into groups having chains of identical length. The method includes performing collision detection between the repair information in each of the groups. The method includes merging the repair information in each of the groups. The method includes repairing the embedded memories using the merged repair information.

A memory device includes a latch circuit suitable for storing an input address as a first latch address in response to a first latch signal, and storing an address, selected between the input address and the first latch address, as a second latch address in response to a second latch signal, a test determining circuit suitable for determining whether a memory cell fail occurs, based on test data, and generating a detection signal corresponding to the determination result, in response to a test mode signal, and a control signal generation circuit suitable for comparing the input address to the first and second latch addresses in response to the detection signal, and selectively enabling the first and second latch signals according to the comparison result.

Methods, apparatuses and systems related to managing access to a memory device are described. A memory device includes fuses and latches for storing a repair segment locator and a repair address for each repair of one or more defective memory cells. A segment-address determination circuit generate an active segment address based on the repair address according to the repair segment locator and an address for a read or a write operation. A comparator circuitry is configured to determine whether the active segment address matches the address for the read or the write operation for replacing the one or more defective memory cells with the plurality of redundant cells when the address for the read/write operation corresponds to the one or more defective memory cells.

An E-fuse circuit comprising: an E-fuse group, comprising a plurality of E-fuse sections, wherein each one of the E-fuse sections comprises a plurality of E-fuses; a multi-mode latch circuit, configured to receive an input signal to generate a first output signal in a burn in mode, and configured to receive an address to be compared to generate a second output signal in a normal mode; a first logic circuit group, configured to receive a first part of bits of the first output signal to generate a control signal in the burn in mode; and a second logic circuit group, configured to receive the control signal and a second part of bits of the first output signal to generate a selection signal in the burn in mode, to select which one of the E-fuse sections is activated.

A memory-testing circuit configured to perform a test of a memory comprising error-correcting code circuitry comprises repair circuitry configured to allocate a spare row or row block in the memory for a defective row or row block in the memory, a defective row or row block being a row or row block in which a memory word has a number of error bits greater than a preset number, wherein the test of the memory comprises: disabling the error-correcting code circuitry, performing a pre-repair operation, the pre-repair operation comprising: determining whether the memory has one or more defective rows or row blocks, and allocating one or more spare rows or row blocks for the one or more defective rows or row blocks if the one or more spare rows or row blocks are available, and performing a post-repair operation on the repaired memory.

Methods, apparatuses and systems related to managing access to a memory device are described. A memory device includes fuses and latches for storing a repair segment locator and a repair address for each repair of one or more defective memory cells. A segment-address determination circuit generate an active segment address based on the repair address according to the repair segment locator and an address for a read or a write operation. A comparator circuitry is configured to determine whether the active segment address matches the address for the read or the write operation for replacing the one or more defective memory cells with the plurality of redundant cells when the address for the read/write operation corresponds to the one or more defective memory cells.

A memory device includes a memory bank accessible via a plurality of memory addresses. The memory device further includes a fuse array including a plurality of fuse banks. A fuse bank of the plurality of fuse banks includes a fuse circuit, which includes a fuse latch having first input circuitry. The fuse latch is implemented to store a first bit of a first memory address received at the first input circuitry. The fuse circuit also includes a matching circuit coupled to the first input circuitry. The matching circuit is implemented to receive a first bit of a second memory address at the first input circuitry and to output, at output circuitry, a comparison result based at least in part on the first bit of the first memory address and the first bit of the second memory address.

A system includes a processor and a memory set coupled to the processor. The system also includes a repair circuit coupled to the memory set. The repair circuit includes a first repair circuit and a second repair circuit. The repair circuit also includes a test controller configured to select between the first repair circuit and the second repair circuit to perform an in-field self-repair of the memory set.

A memory device includes a memory bank accessible via a plurality of memory addresses. The memory device further includes a fuse array including a plurality of fuse banks. A fuse bank of the plurality of fuse banks includes a fuse circuit, which includes a fuse latch having first input circuitry. The fuse latch is implemented to store a first bit of a first memory address received at the first input circuitry. The fuse circuit also includes a matching circuit coupled to the first input circuitry. The matching circuit is implemented to receive a first bit of a second memory address at the first input circuitry and to output, at output circuitry, a comparison result based at least in part on the first bit of the first memory address and the first bit of the second memory address.