The present disclosure relates to a memory architecture comprising a plurality of subarrays of memory cells, a plurality of sense amplifiers connected to the subarrays, a plurality of original pads, at least one redundant pad, multiple data lines, and a redundant register connected to the plurality of original pads, to the plurality of redundant pads and to the data lines. The redundant register implementing an interconnection redundancy and connecting one of the redundant pads to the data lines when an addressed original pad is found defective. The disclosure also relates to a System-on-Chip (SoC) component comprising a memory architecture, and an interconnection redundancy managing block included into the memory architecture. A related memory component and related methods for managing interconnection redundancy of the memory architecture and/or the SoC are also disclosed.

Apparatuses, systems, and methods to perform continuous read operations are described. A system configured to perform such continuous read operations enables improved access to and processing of data for performance of associated functions. For instance, one apparatus described herein includes a memory device having an array that includes a plurality of pages of memory cells. The memory device includes a page buffer coupled to the array and a continuous read buffer. The continuous read buffer includes a first cache to receive a first segment of data values and a second cache to receive a second segment of the data values from the page buffer. The memory device is configured to perform a continuous read operation on the first and second segments of data from the first cache and the second cache of the continuous read buffer.

Apparatuses and methods of sharing error correction memory on an interface chip are described. An example apparatus includes: at least one memory chip having a plurality of first memory cells and an interface chip coupled to the at least one memory chip and having a control circuit and a storage area. The control circuit detects one or more defective memory cells of the first memory cells of the at least one memory chip. The control circuit further stores first defective address information of the one or more defective memory cells of the first memory cells into the storage area. The interface chip responds to the first defective address information and an access request to access the storage area in place of the at least one memory chip when the access request has been provided with respect to the one or more defective memory cells of the first memory cells.

A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

A memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

A memory device with built-in flexible redundancy is provided according to various aspects of the present disclosure. In certain aspects, a memory device includes a first sense amplifier, a second sense amplifier, a first comparator, a second comparator, a reference circuit, and a logic gate. During a redundant read operation, the first sense amplifier, the first comparator, and the reference circuit are used to read one copy of a redundant bit stored in the memory device, and the second sense amplifier, the second comparator, and the reference circuit are used to read another copy of the redundant bit stored in the memory device. The logic gate may then determine a bit value based on the bit values of the read copies of the redundant bit (e.g., determine a bit value of one if the bit value of at least one of the read copies of the redundant bit is one).

Embodiments of the disclosure are drawn to apparatuses and methods for dynamic column select swapping. A memory may have a number of sets of bit lines organized into column planes. If a set of bit lines associated with a first address in a first column plane is defective, it may be repaired by reassigning the first address to a redundant set of bit lines in a global column redundant (GCR) column plane. If a set of bit lines associated with the first address in a second column plane is also defective, then swap logic of the memory may swap the first address to a second address and assign it to the set of bitlines in the second column plane. The second address may then also be repaired by being reassigned to the GCR column plane.

The present disclosure relates to a memory architecture comprising a plurality of subarrays of memory cells, a plurality of sense amplifiers connected to the subarrays, a plurality of original pads, at least one redundant pad, multiple data lines, and a redundant register connected to the plurality of original pads, to the plurality of redundant pads and to the data lines. The redundant register implementing an interconnection redundancy and connecting one of the redundant pads to the data lines when an addressed original pad is found defective. The disclosure also relates to a System-on-Chip (SoC) component comprising a memory architecture, and an interconnection redundancy managing block included into the memory architecture. A related memory component and related methods for managing interconnection redundancy of the memory architecture and/or the SoC are also disclosed.

A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

Embodiments of the present invention facilitate efficient and effective increased memory cell density configuration. In one embodiment, a memory system comprises: an array of addressable memory cells, wherein the addressable memory cells of the array comprise magnetic random access memory (MRAM) cells and wherein further the array is organized into a plurality of banks; an engine configured to control access to the addressable memory cells organized into the plurality of banks; and a pipeline configured to perform access control and communication operations between the engine and the array of addressable memory cells. At least a portion of operations associated with accessing at least a portion of one of the plurality of memory banks via the pipeline are performed substantially concurrently or in parallel with at least a portion of operations associated with accessing at least another portion of one of the plurality of memory banks via the pipeline.