A memory device is disclosed, including a memory array and a selection circuit. At least one first faulty cell and at least one second faulty cell that are in the memory array store data corresponding to, respectively, first and second fields of a floating-point number. The selection circuit identifies the at least one first faulty cell and the at least one second faulty cell based on a priority of a cell replacement operation which indicates that a priority of the at least one first faulty cell is higher than that of the at least one second faulty cell. The selection circuit further outputs a fault address of the at least one first faulty cell to a redundancy analyzer circuit for replacing the at least one first faulty cell.

A determination is made by a processing device included in a memory component that an operation to program data to a location in the memory component has failed, the data is programmed to a different location in the memory component by the processing device upon determining the operation has failed, and a notification that the data has been programmed to the different location in the memory component is provided by the processing device to a processing device operatively coupled to the memory component.

A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die, a volatile memory die, and a logic die. The non-volatile memory die, the volatile memory die, and the logic die are stacked. The 3D SIC is partitioned into a plurality of columns that are perpendicular to each of the stacked dies. Each column of the plurality of columns is configurable to be bypassed via configurable routes. When the configurable routes are used, functionality of a failing part of the column is re-routed to a corresponding effective part of a neighboring column.

A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die, a volatile memory die, and a logic die. The non-volatile memory die, the volatile memory die, and the logic die are stacked. The 3D SIC is partitioned into a plurality of columns that are perpendicular to each of the stacked dies. Each column of the plurality of columns is configurable to be bypassed via configurable routes. When the configurable routes are used, functionality of a failing part of the column is re-routed to a corresponding effective part of a neighboring column.

Apparatuses and techniques are described for reliably storing bad column data in a memory device. Units of bad column data and related units of error detection data are stored in non-adjacent groups of memory cells connected to a word line in a ROM block. A unit of bad column data and a related unit of error detection data can be stored in respective groups of memory cells which are relatively far apart from one another along the word line. This helps ensure that a defect in some NAND strings will not affect both the unit of bad column data and a related unit of error detection data. In another aspect, a unit of bad column data and a related unit of error detection data can be stored using different input/output circuits to further increase robustness.

A determination is made by a processing device included in a memory component that an operation to program data to a location in the memory component has failed, the data is programmed to a different location in the memory component by the processing device upon determining the operation has failed, and a notification that the data has been programmed to the different location in the memory component is provided by the processing device to a processing device operatively coupled to the memory component.

A read path for a memory is provided that includes an integrated sense mixing and redundancy shift stage coupled between a sense amplifier and a data latch. The data latch is integrated with a level shifter.

A determination is made by a processing device included in a memory component that an operation to program data to a location in the memory component has failed, the data is programmed to a different location in the memory component by the processing device upon determining the operation has failed, and a notification that the data has been programmed to the different location in the memory component is provided by the processing device to a processing device operatively coupled to the memory component.

A read path for a memory is provided that includes an integrated sense mixing and redundancy shift stage coupled between a sense amplifier and a data latch. The data latch is integrated with a level shifter.

A read path for a memory is provided that includes an integrated sense mixing and redundancy shift stage coupled between a sense amplifier and a data latch. The data latch is integrated with a level shifter.