Provided is a method of detecting a defective layer. A method, performed by a computing system, of detecting a defective layer of a semiconductor device including a plurality of layers includes obtaining candidate defective layer information regarding a plurality of candidate defective layers and obtaining physical structure information regarding the candidate defective layers, dividing each of wires in the candidate defective layers into virtual micro areas based on the candidate defective layer information and based on the physical structure information, and identifying a defective layer from among the candidate defective layers according to a number of the virtual micro areas.

Computer-based simulation of a device under test (DUT) corresponding to a user circuit design includes providing an adapter configured to couple to the DUT during the computer-based simulation (simulation). The adapter is configured to translate incoming high-level programming language (HLPL) transactions into DUT compatible data for conveyance to the DUT and translate DUT compatible data generated by the DUT to outgoing HLPL transactions. A communication server is provided that couples to the adapter during the simulation. The communication server is configured to exchange the incoming and outgoing HLPL transactions with an entity executing external to the simulation. A communication layer client is provided that is configured to execute external to the simulation and exchange the incoming and outgoing HLPL transactions with the communication server. The communication layer client provides an application programming interface through which an external computer program generates data traffic to drive the DUT within the simulation.

A method for a fault ride through testing of an electrical system including one or more power sources, one or more power consumers, and a first protective-isolation device and a second protective-isolation device both disposed between the one or more power sources and the one or more power consumers is disclosed. The method includes prior to the fault ride through testing, opening the second protective-isolation device, and closing the first protective-isolation device, and during the fault ride through testing, opening both the first and second protective-isolation devices to block current flow between the one or more power sources and the one or more power consumers. The method also includes during the fault ride through testing, decreasing a terminal voltage of the one or more power sources using a voltage regulator, and following the fault ride through testing, opening the first protective-isolation device, and closing the second protective-isolation device.

Aspects provide for dynamic pathloss mitigation via a cross layer tool chain by simulating a three-dimensional model of a physical environment including an access point, an endpoint running an application, and a passive object; emulating network traffic for the application transmitted between the access point and the endpoint; simulating, in the model, pathways for signals to carry the traffic in a plurality of regions for the physical environment; emulating signal degradation along the pathways in the plurality of regions based on respective locations for the access point, the endpoint, and the passive object in the physical environment; and in response to the signal degradation satisfying a pathloss threshold, outputting a command to the application to affect operations of the endpoint. Additionally, the cross layer tool chain outputs a Graphical User Interface showing a signal degradation map based on the simulated network traffic overlaid on the model.

A battery emulation apparatus for supplying a device-under-test (DUT) with electrical power, comprising output terminals for connecting the DUT and an output voltage module providing a variable DC output voltage. A user interface receives a user input comprising the setting of battery parameter(s) and measurement criteria. A data storage stores data representing battery models. A processor selects a battery model based on the parameter(s) and controls the output voltage module to emulate characteristics of the selected battery model(s) according the data, while supplying the DUT with the output voltage. The processor monitors a response of the DUT and/or the output voltage module to the emulated characteristics of the selected battery model(s), wherein the response comprises a physical measurement value. The processor evaluates said physical measurement value based on the set measurement criteria in order to assess the suitability of the selected model(s).

A method for predicting a defect in a semiconductor device includes: calculating a first probability that particles will be generated in a semiconductor element by radiation; calculating a second probability that damage will occur in the semiconductor element due to the particles; generating a training data set using input data and simulation data, the input data including damage data generated using the first probability and the second probability and including at least one of a position in which the damage will occur and an amount of the damage, impurity concentration of impurities doped in at least a portion of the semiconductor element, and structural data of the semiconductor element, and the simulation data including electrical characteristics of the semiconductor element obtained as a result of a simulation based on the input data; and training a machine learning model based on the training data set to generate a defect prediction model.

A hardware-in-the-loop (HIL) simulation device is provided, which includes a processing circuit and a pulse-width modulation (PWM) signal observation circuit. The PWM signal observation circuit includes an energy storage unit and the energy storage unit is coupled to the processing circuit. A signal source transmits a PWM signal to the processing circuit and the PWM signal observation circuit, and the energy storage unit is charged when the PWM signal is at high level. The processing circuit detects the voltage of the energy storage unit when detecting the falling edge of the PWM signal so as to calculate the duty cycle of the PWM signal.

A method for predicting failure parameters of semiconductor devices can include receiving a set of data that includes (i) characteristics of a sample semiconductor device, and (ii) parameters characterizing a stress condition. The method further includes extracting a plurality of feature values from the set of data and inputting the plurality of feature values into a trained model executing on the one or more processors, wherein the trained model is configured according to an artificial intelligence (AI) algorithm based on a previous plurality of feature values, and wherein the trained model is operable to output a failure prediction based on the plurality of feature values. Further, the method includes generating, via the trained model, a predicted failure parameter of the sample semiconductor device due to the stress condition.

A DC/DC converter fault diagnosis method based on an improved sparrow search algorithm, includes: establishing an simulation module of the converter, selecting a leakage inductance current of a transformer as a diagnosis signal, and collecting diagnosis signal samples under OC faults of different power switching devices of the converter as a sample set; improving a global search ability of a sparrow search algorithm by using a Levy flight strategy; dividing the sample set into a training set and a test set, preliminarily establishing an architecture of a deep belief network, and initializing network parameters; optimizing a quantity of hidden-layer units of the deep belief network by using an improved sparrow search algorithm, to obtain a best quantity of hidden-layer units of the deep belief network; and training an optimized deep belief network obtained based on the improved sparrow search algorithm, and obtaining a fault diagnosis result based on a trained network.

A testing structure is disclosed. The testing structure includes a first layer, a second layer, and a third layer. The first layer includes a first pattern. The third layer includes a second pattern. The first layer, the second layer, and the third layer overlap each other. The second layer is connected to a CBCM (charged based capacitance measurement) testing circuit.