The invention provides a semiconductor testkey pattern, the semiconductor testkey pattern includes a high density device region and a plurality of resistor pairs surrounding the high density device region, wherein each resistor pair includes two mutually symmetrical resistor patterns.

A system and method for die crack detection in a CMOS bonded array includes a capacitor that is formed in an edge seal, where one of the capacitor plates is in the edge seal portion of a first wafer, and the other capacitor plate is in the edge seal portion of a second wafer. A crack in the die can be detected by applying an alternating current waveform to a testing contact on the integrated circuit and monitoring for a shift in the alternating current waveform, as a crack would cause modulation in the capacitance.

A system and method for updating power supply voltages due to variations from aging are described. A functional unit includes a power supply monitor capable of measuring power supply variations in a region of the functional unit. An age counter measures an age of the functional unit. A control unit notifies the power supply monitor to measure an operating voltage reference. When the control unit receives a measured operating voltage reference, the control unit determines an updated age of the region different from the current age based on the measured operating voltage reference. The control unit updates the age counter with the corresponding age, which is younger than the previous age in some cases due to the region not experiencing predicted stress and aging. The control unit is capable of determining a voltage adjustment for the operating voltage reference based on an age indicated by the age counter.

A method of obtaining a physical property of a test sample, comprising a conductive or semi-conductive material (line/area/volume), by performing electric measurements using a multi-terminal microprobe. Periodic Joule heating within the test sample is induced by passing an ac current across a first pair of probe terminals electrically connected to the test sample, measuring the voltage at one and three times the power supply frequency of the current-conducting terminals across a second pair of probe terminals electrically connected to the test sample, and calculating the temperature-modulated property(ies) of the test sample as a function of the voltage measurements at said frequencies. A value proportional to the Temperature Coefficient of Resistivity (TCR), an Electrical Critical Dimension (ECD), or the true resistivity of the test sample at the ambient experimental temperature by subtracting a measurable TCR offset from the apparent (heating-affected) resistivity of the test sample can be determined.

A method for evaluating a Hot Carrier Injection (HCI) effect of a device is provided. The method includes, a ratio of a substrate current to a drain current of a first device at different gate-source voltages is acquired, and recorded as a first current ratio; a ratio of a substrate current to a drain current of a second device at different gate-source voltages is acquired, and recorded as a second current ratio, the second device is subjected to process parameter adjustment or device parameter adjustment relative to the first device; and an influence of the process parameter adjustment or the device parameter adjustment on an HCI effect of the device is determined based on the second current ratio and the first current ratio.

A physical property of a test sample with a conductive or semi-conductive material (line/area/volume) is obtained. Periodic Joule heating is induced within the test sample by passing an AC current across a first pair of probe terminals electrically connected to the test sample, measuring the voltage drop across a second pair of probe terminals electrically connected to the test sample at one and three times the fundamental excitation frequency of the current-conducting terminals, and calculating the temperature-modulated property/properties of the test sample as a function of the potential drop measurement(s). This includes: a) determining a value proportional to the TCR of the test sample, b) a geometric parameter of the test sample (affected by coupling of its TCR to heat transport to/from the test sample), or c) the true resistivity of the test sample at the ambient experimental temperature by subtracting measurable and accountable TCR offset(s).

A test circuit includes one or more sensors adapted to be formed on a wafer, each sensor detecting one or more reliability measurement data in a stressed condition; a stress generator controlling the one or more sensors to place the one or more sensors under stress during wafer manufacturing; memory coupled to the one or more sensors to store reliability characteristics under the stressed condition; and an interface coupled to the memory to communicate the wafer characterization data to a tester.

An electromigration (EM) test structure for localizing EM-induced voids is provided. The EM test structure includes an EM test element, a via, and a stress line. The EM test element includes a first force pad and a first sense pad. The via electrically connects the EM test element to the stress line. A second end portion of the stress line includes a second force pad and a second sense pad. The second force pad defines, at least in part, a conductive pathway between the first and second force pads. The second sense pad defines, at least in part, a conductive pathway between the first and second sense pads to facilitate four-terminal resistance measurements. A first end portion of the stress line includes a third sense pad that defines, at least in part, a conductive pathway between the first and third sense pads to facilitate four-terminal resistance measurements.

Various embodiments provide a health monitor circuit including an n-type sensor to determine a first health indicator associated with n-type transistors of a circuit block and a p-type sensor to determine a second health indicator associated with p-type transistors of the circuit block. The n-type sensor and p-type sensor may be on a same die as the circuit block. The health monitor circuit may further include a control circuit to adjust one or more operating parameters, such as operating voltage and/or operating frequency, for the circuit block based on the first and second health indicators. Other embodiments may be described and claimed.

Provided is a semiconductor device that can detect the cracking progress with high precision. A semiconductor device is formed using a semiconductor substrate, and includes an active region in which a semiconductor element is formed, and an edge termination region outside the active region. A crack detection structure is termed in the edge termination region of the semiconductor substrate. The crack detection structure includes: a trench formed in the semiconductor substrate and extending in a circumferential direction of the edge termination region; an inner-wall insulating film formed on an inner wall of the trench; an embedded electrode formed on the inner-wall insulating film and embedded into the trench; and a monitor electrode formed on the semiconductor substrate and connected to the embedded electrode.