An opening/closing mechanism of a cover member that can easily push down the cover member by the lever member even if the force from the base member side to the cover member is increased, improving the operability of the lever member. A solution is that the lever member 17 is rotatably supported to the base member 23 by the first shaft 31, the link plate 29 is mounted to the lever member 17 by the second shaft 32, the cover member 15 is mounted to the link plate 29 by the third shaft 33, and the link plate 29 is rotated around the axis of the first shaft 31 in the direction in which the lever member 17 closes, so that the link plate 29 moves through the second shaft 32, and the link plate 29 moves, so that the cover member 15 is depressed through the third shaft 33.

A test apparatus includes a motherboard including a first surface. The test apparatus further includes a handler including a second surface facing the first surface of the motherboard. The test apparatus additionally includes an adapter board disposed between the first surface of the motherboard and the second surface of the handler. The test apparatus further includes a first sensor mounted on the adapter board and senses data about temperature of the adapter board. The test apparatus additionally includes a wireless transceiver mounted on the adapter board and transmits, in real time, the sensed data.

An apparatus for testing integrated circuits (ICs) , includes a first thermal contact structure having a first surface to interface with a heat source and an opposing second surface to interface with a device under test (DUT). A second thermal contact structure is above the first thermal contact structure and separated therefrom by a variable-resistance thermal interface (VRTI) structure operable to couple or decouple the first and second thermal contact structures from one another. The VRTI structure has a maximal thermal conductivity associated with a first state, and a minimal thermal conductivity associated with a second state.

Methods and apparatus of forming a thermal interface with condensate are described. In an example, a device may be disposed in a test environment or a test apparatus. An amount of condensate may be accumulated on a heat sink to coat the heat sink with a layer of condensate. The coated heat sink may be disposed on the device, where the layer of condensate is directed towards the device, and the disposal of the coated heat sink causes the layer of condensate to spread among voids between the heat sink and the device to form a thermal interface that includes the condensate. A test may be executed on the device with the thermal interface comprising the condensate between the coated heat sink and the device.

A test board for testing a semiconductor apparatus includes a first board configured to support a plurality of first Devices Under Test (DUTs) such that the plurality of first DUTs are mounted on the first board, a plurality of first inter-board connectors arranged on the first board, and a plurality of second boards stacked on the first board through the plurality of first inter-board connectors, each second board of the plurality of second boards having a surface configured to support a separate second DUT of a plurality of second DUTs such that the plurality of second DUTs are mounted on separate, respective second boards of the plurality of second board.

A testing apparatus comprises a tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises: (a) an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT); and (b) a carrier comprising an array of DUTs, wherein the carrier is operable to displace into the slot of the rack; and (c) an array of POP memory devices, wherein each POP memory device is disposed adjacent to a respective DUT in the array of DUTs. Further, the testing apparatus comprises a pick-and-place mechanism for loading the array of DUTs into the carrier and an elevator for transporting the carrier to the slot of the rack.

A probe card includes a sub-board, having a heating layer, connected to a probe pin. A main board is connected to the sub-board and includes a first output terminal configured to output first power received from a first power supply to the heating layer in a first mode. A power converter is configured to lower a first voltage corresponding to residual power received from the first power supply to a second voltage and output the residual power in a second mode. A second output terminal is configured to receive the residual power from the power converter and second power from a second power supply and output third power including the residual power and the second power to a device under test in the second mode. A first switch unit is connected to the first power supply, the first output terminal, and the power converter.

The present invention relates to a test socket having a thin structure that can reduce durability degradation of a contact itself, have excellent electrical characteristics in processing high-speed signals, and can extend a service life thereof, and relates to spring contacts suitable thereto. The test socket according to the present invention includes: a plurality of spring contacts (100) each of which includes an upper contact pin (110) and a lower contact pin (120) that are assembled cross each other, and a spring (130) supporting the upper and lower contact pins (110 and 120); a main plate (1110) having a plurality of accommodating holes (1111) in which the respective spring contacts (100) are accommodated, with first openings (1113); and a film plate (1120) provided on a lower portion of the main plate (1110), and having second openings (1121).

A reduced pin count (RPC) device includes an electrical circuitry in a package with uniformly distributed leads, a subset of the leads being electrically disconnected form the circuitry. A contactor pin block with sockets corresponding to the uniformly distributed leads has the sockets corresponding to the leads with electrical connections filled with test pins suitable for contacting respective leads, and the sockets corresponding to the electrically disconnected leads voided of test pins. Dummy plugs are inserted into the voided sockets to block the sockets and prevent accidental insertions of test pins.

The present invention provides a device for testing a chip, wherein the device includes a testing board and an interposer. The testing board has a plurality of pads for providing a plurality of test signals. The interposer board includes a plurality of passive components, and at least one of the passive components is coupled between a supply voltage and a ground voltage, and the supply voltage and the ground voltage are received from a power pad and a ground pad of the plurality of pads of the testing board, respectively; wherein the chip is positioned in the device, the chip receives the test signals including the supply voltage and the ground voltage from the power pad and the ground pad of the testing board, respectively.