An apparatus has a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines. Selection circuitry is positioned within the scribe lines. The selection circuitry is connected to test circuits in the scribe lines. The selection circuitry operates to enable voltage control at a single test circuit while disabling all other test circuits.

A test board includes a board substrate, a connector at a side of the board substrate, a plurality of device-under-test (DUT) boards which are connected to the board substrate and on which semiconductor devices are mounted as DUTs, and a plurality of DC-DC converters connected to the plurality of DUT boards. The plurality of DC-DC converters convert an input voltage supplied thereto via the connector into operating voltages, and provide the operating voltages to the semiconductor devices on the plurality of DUT boards corresponding thereto. The operating voltages are substantially the same.

The present disclosure relates to a through-silicon via (TSV) crack detecting apparatus, a detecting method, and a fabricating method of the semiconductor device. The TSV crack detecting apparatus includes a test TSV, a conductive liner, a second dielectric liner, a first contact, and a second contact. The test TSV is disposed within a semiconductor substrate, including a conductive channel and a first dielectric liner for isolating the conductive channel and the semiconductor substrate. The conductive liner surrounds the first dielectric liner. The second dielectric liner surrounds the conductive liner. The first contact is connected to the conductive channel. The second contact is connected to the conductive liner. A voltage difference between the first contact and the second contact is used to determine whether a TSV within a predetermined range to the test TSV has a crack based on a conductive state between the first contact and the second contact.

Circuitry, systems, and methods for fault detection and reporting comprise a fault detection circuit configured to detect one or more fault conditions that cause a state change in a fault pin voltage representative of a transceiver failure. Once the state of the fault pin voltage changes, a transceiver input generates a fault detection code. In embodiments, in response to the transceiver input receiving a first signal, the fault detection code is shifted to a transceiver output that may communicate the fault detection code to a controller. Once the transceiver input receives a second signal, the fault pin voltage may be reset to clear the fault detection code before resuming operations, including detecting additional fault conditions as they arise.

Two approaches for on-chip ESD detection include variable dielectric width capacitor, and vertical metal-oxide-semiconductor (MOS) capacitor MOSCAP array. The variable dielectric width capacitor approach employs metal plates terminated with sharp corners to enhance local electric field and facilitate ready breakdown of a thin dielectric between the metal plates. The vertical MOSCAP array is composed of a capacitor array connected in series. Both approaches are incorporated in an example 22 nm fully depleted silicon-on-insulator. Vertical MOSCAP arrays detect ESD events starting from about 6 V with about 6 V granularity, while the variable dielectric width capacitor is suitable for detection of high ESD voltage from about 40 V and above.

A power management device and microprocessor within a System-in-Package (SiP) are provided with communication signals externally available as outputs from the SiP so that they can be reconfigured by an external device. Methods for the configuration of SiPs and Power Management Integrated Circuits (PMICs) packaged within a SiP are also provided.

Circuits and methods for improving IC yield during automated test equipment (ATE) calibration of circuit designs which require I.sub.DD calibration and use a closed feedback bias circuit, such as amplifier circuits. The circuit designs include bias branch/active circuit architectures where the active circuit includes one or more active devices. An example first embodiment uses an on-chip calibration switch between the on-chip grounds of a bias network and an active circuit comprising an amplifier. During calibration of the active circuit by the ATE, the calibration switch is closed, and after completion of calibration, the calibration switch is opened. An example second embodiment utilizes an active on-chip feedback loop calibration circuit to equalize voltages between the on-chip grounds of a bias network and an active circuit comprising an amplifier during calibration of the active circuit. Both embodiments mitigate or overcome miscalibration of active circuit current settings resulting from ATE test probe resistance.

A semiconductor device with contact check circuitry is provided. The semiconductor device includes a plurality of pads, an internal circuit, and a contact check circuit. The plurality of pads includes a first pad and a second pad. The internal circuit is coupled to the plurality of pads. The contact check circuit, at least coupled to the first pad and the second pad, is used for checking, when the semiconductor device is under test, contact connections to the first pad and the second pad to generate a check result signal according to comparison of a first test signal and a second test signal received from the first pad and the second pad with at least one reference signal.

A voltage tracking circuit includes first, second, third and fourth transistors. The first transistor is in a first well, and includes a first gate, a first drain and a first source coupled to a first voltage supply. The second transistor includes a second gate, a second drain and a second source. The second source is coupled to the first drain. The second gate is coupled to the first gate and the pad voltage terminal. The third transistor includes a third gate, a third drain and a third source. The fourth transistor includes a fourth gate, a fourth drain and a fourth source. The fourth drain is coupled to the third source. The fourth source is coupled to the pad voltage terminal. The fourth transistor is in a second well different from the first well, and is separated from the first well in a first direction.

A test system may be used for obtaining accurate remote sense voltage and/or current values. A measurement instrument may provide a regulated stimulus signal to a device under test (DUT) and measure a DUT signal developed at least partially in response to the stimulus signal. A test circuit may superimpose a test signal over the stimulus signal to cause the DUT signal to be developed further in response to the test signal. The DUT signal may be used to derive a resistance of the path that couples the measurement instrument to the DUT. The measurement instrument may include a source measure unit, the stimulus signal may be a regulated voltage, and the DUT signal may be a sense voltage. The harmonics of the DUT signal may be analyzed to determine a correlation between an amplitude of a measured fundamental frequency of the DUT signal and the resistance of the path.