A test board for testing a semiconductor apparatus includes a first board configured to support a plurality of first Devices Under Test (DUTs) such that the plurality of first DUTs are mounted on the first board, a plurality of first inter-board connectors arranged on the first board, and a plurality of second boards stacked on the first board through the plurality of first inter-board connectors, each second board of the plurality of second boards having a surface configured to support a separate second DUT of a plurality of second DUTs such that the plurality of second DUTs are mounted on separate, respective second boards of the plurality of second board.

A semiconductor device test apparatus for improving a loss rate of a test signal in testing a device under test is provided. The semiconductor device test apparatus includes a probe interface board, a pogo block disposed on the probe interface board and electrically connected to a device under test, an equipment board disposed under the probe interface board, an alternating current (AC) controller, transferring and receiving an AC signal for performing an AC test on at least one of the device under test and the pogo block, being mounted on the equipment board, and a physical layer equalizing (PLE) board disposed between the probe interface board and the equipment board, a first equalizing circuit, decreasing loss of the AC signal, being mounted on the PLE board.

A semiconductor integrated circuit (IC) comprising a time-to-digital converter (TDC) configured to measure an input-to-output delay of an I/O buffer of a pad the IC, the measured delay reflecting a connection impedance of the pad. A circuit in the IC, or a computer in communication with the IC, determines electrical connection integrity of the pad based on the measured delay of the I/O buffer.

Methods and apparatus relating to processor and chipset continuity testing of package interconnect for functional safety applications are described. In an embodiment, voltage divider logic circuitry divides a reference voltage. Controller logic circuitry compares a divided voltage value from a node of the voltage divider logic circuitry and a threshold voltage value. A first end of the voltage divider logic circuitry is coupled to receive the reference voltage and a second end of the voltage divider logic circuitry is coupled to a Non-Critical-To-Function (NCTF) solder ball. The controller logic circuitry generates an error signal in response to a mismatch between the divided voltage value and the threshold voltage value. Other embodiments are also disclosed and claimed.

An over-the-air (OTA) measurement system is described. The OTA measurement system includes a plurality of measurement antennas, a DUT positioner, and a controller (e.g., control circuit). The DUT positioner is configured to position a device under test at a test location. At least two measurement antennas of the plurality of measurement antennas are arranged at different distances from the test location. The at least two measurement antennas are arranged at different elevation angles and/or at different azimuth angles with respect to the test location. The controller is configured to control the DUT positioner to rotate the device under test at the test location in azimuth and/or elevation. The controller is configured to control the DUT positioner to rotate the device under test into a first orientation for a first OTA power measurement by a first one of the at least two measurement antennas. The controller is configured to control the DUT positioner to rotate the device under test into a second orientation for a second OTA power measurement by a second one of the at least two measurement antennas. A relative orientation between the device under test in the first orientation and the first one of the at least two measurement antennas is the same as a relative orientation between the device under test in the second orientation and the second one of the at least two measurement antennas. Further, an OTA measurement method for performing OTA measurements on a device under test by an OTA measurement system is described.

A wafer inspection system and a wafer inspection equipment thereof are provided. The wafer inspection system includes a susceptor device, probe card, and bridge module. The susceptor device includes a susceptor unit for placing a wafer under test. The probe card includes a probing portion and conducting portion. The conducting portion is disposed at the periphery of the probing portion and has a contact surface. The bridge module includes transmission units extended upward, positioned adjacent to a wafer placement area, and coupled to the susceptor unit. When the probing portion comes into contact with a testing point of the wafer, the contact surface of the conducting portion gets coupled to the transmission units to transmit a test signal to the probe card via the transmission units and conducting portion and thus form a test loop. Thus, the test loop path can be shortened and the accuracy of signal transmission and inspection can be enhanced.

In some examples, a circuit may be configured to perform a method that includes performing a circuit function via a circuit function unit of a circuit, receiving sensor data from one or more sensors associated with the circuit function unit, and estimating a remaining life of the circuit based on an accelerated reliability model and the sensor data, wherein the sensor data comprises input to the accelerated reliability model. The circuit itself may include a dedicated circuit unit that estimates the remaining life of the circuit based on an accelerated reliability model and the sensor data, and the circuit may output one or more predictive alerts or predictive faults when the remaining life is below a threshold, which may prompt the system for predictive maintenance on the circuit.

An testing method includes following operations: generating, by a signal generator, a multi-tone signal; transmitting, by the signal generator, the multi-tone signal to an input terminal of an under-test device; measuring, by a spectrum analyzer, the input terminal of the under-test device and an output terminal of the under-test device to acquire a plurality of input ripple intensities corresponding to a plurality of frequencies and acquire a plurality of output ripple intensities corresponding to the frequencies; and generating, by a control device, a plurality of power supply rejection ratios corresponding to the frequencies according to the input ripple intensities and the output ripple intensities.

The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an IC formed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal is applied to the IC. The stress signal includes a plurality of sequences during a second period subsequent to the first period. Each of the sequence has a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level. Whether the IC complies with a test criterion is determined after applying the stress signal.

Embodiments described herein generally relate to measuring and evaluating a test signal generated by a device under test (DUT). In particular, the test signal generated by the DUT may be compared to a reference signal and scored based on the comparison. For example, a method may include: capturing a test signal from a device under test; splicing the test signal into a plurality of test audio files based on a plurality of frequency bins; at each frequency bin, comparing each of the plurality of test audio files to a corresponding reference audio file from among a plurality of reference audio files, the plurality of reference audio files being associated with a reference signal; and calculating a performance score of the device under test based on the comparisons.