An on-die early lifetime failure detection system with a reliability mechanism isolation circuit provides an early lifetime failure detection. The system measures and monitors reliability at time-0 (t0) and end-of-life. The measurements enable detection of latent reliability or marginality issues during the lifetime of the product. The system includes: a stress controller to adjust voltage for a power supply and voltage for a ground supply in accordance with one or more sensors; and an aging detector circuitry coupled to the stress controller, wherein the aging detector circuitry comprises a ring oscillator having delay stages, wherein each delay stage comprises an aging monitor circuitry, wherein the stress controller to adjust voltage for a power supply and voltage for a ground supply of the delay stage.

An IC includes a plurality of pads at a top surface of a semiconductor wafer, an amplifier configured to receive a first AC signal at an input terminal, and output a second AC signal at an output terminal, a first detection circuit coupled to the input terminal and configured to output a first DC voltage to a first pad of the plurality of pads responsive to the first AC signal, and a second detection circuit coupled to the output terminal and configured to output a second DC voltage to a second pad of the plurality of pads responsive to the second AC signal.

Provided is a test method comprising: preparing a plurality of groups for setting, each of which has a plurality of semiconductor devices for setting, and assigning an inspection voltage to each of the respective plurality of groups for setting; performing first testing by applying the assigned inspection voltage to the semiconductor devices for setting, and testing, at a first temperature, the plurality of semiconductor devices for setting included in each of the plurality of groups for setting; performing second testing by testing, at a second temperature different from the first temperature, a semiconductor device for setting having been determined as being non-defective and by detecting a breakdown voltage at which the semiconductor device for setting is broken; acquiring a relationship between the inspection voltage and the breakdown voltage; and setting an applied voltage used when testing a semiconductor device under test at the first temperature, based on the acquired relationship.

An example test system includes a test head, and a device interface board (DIB) configured to connect to the test head. The DIB is for holding devices under test (DUTs). The DIB includes electrical conductors for transmitting electrical signals between the DUTs and the test head. Servers are programmed to function as test instruments. The servers are external to, and remote from, the test head and are configured to communicate signals over fiber optic cables with the test head. The signals include serial signals.

A testing device includes a power supply and a plurality of testing ports. The testing ports are electrically connected to the power supply. Each of the testing ports includes a contact and a current clamper. The contact is configured to electrically couple a device under test (DUT). The current clamper is connected between the power supply and the contact and configured to allow a limited current having a predetermined current value to flow to the contact.

A measurement device is described that comprises a measurement unit configured to perform measurements on an electric signal of a device under test while applying at least one measurement parameter for performing the measurements. The measurement device has an integrated direct current source configured to power the device under test. The measurement device also comprises a monitoring unit configured to monitor at least one monitoring parameter of the direct current source. The measurement device has a control unit configured to control the measurement parameter. Further, a method for measuring a device under test is described.

Embodiments of the present invention provide systems and methods for performing automated device testing at high power using ATI-based thermal management that substantially mitigates or prevents the pads and pins thereof from being burned or damaged. In this way, the lifespan of the testing equipment is improved and the expected downtime of testing equipment is substantially reduced, while also reducing cost of operation.

An example polarity inverter includes multiple contactors, each of which includes switches that are controllable to configure a current path. Each of the multiple contactors includes contacts, which are interleaved such that first contacts to receive voltage having a first polarity alternate with second contacts to receive voltage having a second polarity, where the first polarity and the second polarity are different. The polarity inverter also includes a first conductive plate to connect electrically to each of the first contacts, and a second conductive plate to connect electrically to each of the second contacts. The first conductive plate and the second conductive plate are in parallel. A dielectric material is between the first conductive plate and the second conductive plate.

A signal adjustment device includes a frequency adjustment circuit, a filter circuit, and a power estimation circuit. The frequency adjustment circuit is configured to receive a two-tone signal from a signal generator and to generate a first signal according to the two-tone signal, wherein the signal generator generates the two-tone signal according to a first coefficient and a second coefficient. The filter circuit is configured to filter the first signal, in order to generate a second signal. The power estimation circuit is configured to detect a power of an intermodulation distortion from the third order signal component, which is associated with the two-tone signal, in the second signal, and to adjust at least one of the first coefficient and the second coefficient according to the power, in order to reduce the power.

A burn-in board for testing the operational integrity of memory devices includes local heating elements for each memory device under test. Each socket on the burn-in board may include a pair of opposed latch heads which move between open positions allowing a memory device to be mounted in the socket, and closed positions where the latch heads rest against the memory device to secure the device in the socket. Local heating elements may be integrated into the latch heads to ensure even heating of each memory device in the burn-in board.