According to one embodiment, a semiconductor device includes: a potential supply terminal to which a potential is supplied; a terminal (I/O terminal) for exchanging a signal with an outside; an I/O current detection load circuit electrically connected to the potential supply terminal and the terminal; and a current sensor circuit detecting the I/O current flowing through the I/O current detection load circuit. The current sensor circuit acquires a sensor current proportional to the I/O current and outputs the acquired sensor current as output information, and the I/O current is an abnormal current flowing through the I/O terminal due to at least one of electrostatic discharge and electromagnetic susceptibility and is a current that is greater than a predetermined current and that causes an abnormal state.

The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.

A multi-prober chuck assembly and channel are provided. The multi-prober chuck assembly, according to one embodiment of the present invention, comprises: a chuck for supporting a wafer; a probe card structure coupled to the top part of the chuck; a heater for heating the chuck under the chuck; a conductive guard plate spaced apart from the heater below the heater; and a body part positioned under the chuck so that the heater and the guard plate are positioned inside the body part, wherein the probe card structure and the body part are coupled mechanically to form a cartridge-type structure.

A circuit includes a power transistor having a main current path between a first supply node and an output pin for connecting a load. A resistance formed by a chip metallization is arranged between the main current path of the power transistor and the output pin. The circuit includes a current measuring circuit coupled to the power transistor and including a sense transistor coupled to the power transistor. The current measuring circuit delivers a measurement current representing a load current flowing through the power transistor. An amplifier circuit generates an amplifier output signal representing the voltage across the resistance, and a control circuit outputs a signal representing the measurement current in a first mode and a signal dependent on the amplifier output signal in a second mode.

A semiconductor inspection device includes: a measuring device that supplies power to a semiconductor device and measures the electrical characteristics of the semiconductor device; an optical scanning device that scans the semiconductor device with light intensity-modulated with a plurality of frequencies; a lock-in amplifier that acquires a characteristic signal indicating the electrical characteristics of the plurality of frequency components; and an inspection device that corrects a phase component of the characteristic signal at an arbitrary scanning position with a phase component at a scanning position reflecting the electrical characteristics of a first layer in the semiconductor device as a reference, specifies a phase component of the characteristic signal at a scanning position reflecting the electrical characteristics of a second layer, normalizes the phase component of the characteristic signal at the arbitrary scanning position by using the phase component, and outputs a result based on the normalized phase component.

An apparatus for performing multiple tests on a device under test (DUT) are provided. The apparatus includes at least one non-transitory computer-readable medium having stored thereon computer-executable instructions and at least one processor coupled to the at least one non-transitory computer-readable medium. The computer-executable instructions are executable by the at least one processor and cause the apparatus to perform operations of inputting a plurality of test patterns to a test apparatus, performing each of the plurality of test patterns on the DUT without interruption, and obtaining a respective result for the DUT in response to each of the plurality of test patterns.

An integrated circuit includes an I/O pad and a protection device coupled to the I/O pad and a first supply node. A transient event detector includes a latch; a first transistor having a first current electrode coupled to the I/O pad, a control electrode coupled to a first supply node, and a second current electrode coupled to a data input of the latch, wherein the latch is configured to store an indication that a transient event occurred. An event level sensor includes a first transistor having a first current electrode coupled to the I/O pad, a control electrode coupled to the protection device, and a second current electrode coupled to a load circuit; a rectifier device coupled between the second current electrode and a capacitor; a second transistor having a control electrode coupled to the capacitor; and an output circuit configured to place a current on a first sense bus proportional to a current through the load circuit.

The present disclosure is directed to methods and systems for analyzing integrated circuits. The method includes performing a first resistor capacitor (RC) extraction process on a power-receiving circuit and producing a first RC model. The method also includes scanning a netlist of a power distribution network, the power distribution network electrically connected to the power-receiving circuit. The method further includes determining a selection of circuit elements of the power distribution network based on a predetermined criteria. The method further includes performing a second RC extraction process on the selection of circuit elements and producing a second RC model. The method further includes performing a simulation process on the power-receiving circuit and the power distribution network using the first and second RC models.

A testing system for electrical interconnects having a removable device under test printed circuit board (DUT PCB) that electrically connects with the electrical testing components of the system. A removable top plate is placed on top of the DUT PCB and is locked in place by a plurality of locking posts that selectively connect to cam surfaces in the top plate that pull the top plate down sandwiching the DUT PCB between the top plate and the electrical testing components of the system. An actuator is also presented that presses the device under test into the electrical interconnect at increments where tests are performed on one, some or all of the contact points of the electrical interconnect. This information is then analyzed and graphed to assist with determine the optimum force and/or height to use during actual use.

A degradation detection circuit may include a degradation unit including multiple delay elements driven by a high voltage for degradation. The high voltage for degradation value may be higher than an operation voltage. The degradation unit may be configured to provide a first delayed signal after passing a test signal through the degradation unit, wherein the test signal retains a pulse for a preset time. The degradation detection circuit may include a reference unit including a plurality of delay elements driven by the operation voltage, and configured to provide a second delayed signal after passing the test signal through the reference unit, a delay setting unit configured to provide a third delayed signal by selectively adding delay elements with respect to the second delayed signal, and a delay checking logic configured to detect a delay of the test signal by comparing the first delayed signal and the third delayed signal.