A method for predicting failure parameters of semiconductor devices can include receiving a set of data that includes (i) characteristics of a sample semiconductor device, and (ii) parameters characterizing a stress condition. The method further includes extracting a plurality of feature values from the set of data and inputting the plurality of feature values into a trained model executing on the one or more processors, wherein the trained model is configured according to an artificial intelligence (AI) algorithm based on a previous plurality of feature values, and wherein the trained model is operable to output a failure prediction based on the plurality of feature values. Further, the method includes generating, via the trained model, a predicted failure parameter of the sample semiconductor device due to the stress condition.

A probing system includes a chuck configured to support a device under test (DUT); a probe card disposed above the chuck and including a plurality of probes protruding from the probe card toward the chuck; and a platen disposed between the chuck and the probe card and configured to support the probe card, wherein the chuck includes a shielding member disposed between the platen and the chuck.

Probe systems and methods including active environmental control are disclosed herein. The methods include placing a substrate, which includes a device under test (DUT), on a support surface of a chuck. The support surface extends within a measurement environment that is at least partially surrounded by a measurement chamber. The methods further include determining a variable associated with a moisture content of the measurement environment and receiving a temperature associated with the measurement environment. The methods also include supplying a purge gas stream to the measurement chamber at a purge gas flow rate and selectively varying the purge gas flow rate such that a dew point temperature of the measurement environment is within a target dew point temperature range. The methods further include providing a test signal to the DUT and receiving a resultant signal from the DUT. The systems include probe systems that perform the methods.

Disclosed is a device for testing components under elevated pressure in which a pressure chamber is provided. The lateral boundary of the pressure chamber included a ring and an annular part, which may move perpendicularly to the plane of the component to be tested. A velvet-like lining is provided on the end face of the annular part or of the ring that faces the component to be tested. The fibers of the lining protrude from the annular part or from the ring toward the component to be tested and bridge the gap between the device and the component.

A system for monitoring and controlling an IC testing machine includes a vibration sensor, a sensor interface, and a processor coupled to the sensor interface. The vibration sensor is in mechanical communication with an IC testing machine to develop an electrical vibration signal representing mechanical vibrations generated by the operation of the IC testing machine. The sensor interface processes the vibration signal to develop vibration data that can be processed by the processor to determine whether the vibration data is indicative of an operational anomaly and, if so, to generate a machine control signal to correct an operation of the IC testing machine. Multiple vibration sensors can be used to increase the amount of vibration data available for analysis.

A wafer inspection device 10 is provided with a chuck top 20 on which a wafer W having semiconductor devices formed thereon is placed, a probe card 18 having multiple contact probes 28 protruding toward the wafer W, a pogo frame 23 for holding the probe card 18, a cylindrical internal bellows 26 configured to suspend from the pogo frame 23 to surround the contact probes 28, and a cylindrical external bellows 27 configured to suspend from the pogo frame 23 to surround the internal bellows 26. When the chuck top 20 approaches the probe card 18 and the contact probes 28 are brought into contact with the devices, the internal bellows 26 and the external bellows 27 come in contact with the chuck top 20, a sealing space P is formed between the internal bellows 26 and the external bellows 27, and the sealing space P is compressed.

A testing system includes: an inspection module including a plurality of levels of inspection chambers in each of which a tester part having a tester configured to perform an electrical inspection of an inspection object and a probe card is accommodated; an aligner module configured to align the inspection object with the tester part; an alignment area in which the aligner module is accommodated; and a loader part configured to load the inspection object into the alignment area and unload the inspection object out of the aligner module, wherein the inspection module is located adjacent to the alignment area.

Disclosed is an integrated circuit (IC) comprising a substrate (10) carrying a plurality of circuit elements; a metallization stack (12, 14, 16) interconnecting said circuit elements, said metallization stack comprising a patterned upper metallization layer comprising at least one sensor electrode portion (20) and a bond pad portion (22), at least the at least one sensor electrode portion of said patterned upper metallization layer being covered by a moisture barrier film (23); a passivation stack (24, 26, 28) covering the metallization stack, said passivation stack comprising a first trench (32) exposing the at least one sensor electrode portion and a second trench (34) exposing the bond pad portion; said first trench being filled with a sensor active material (36). A method of manufacturing such an IC is also disclosed.

Probe systems configured to test a device under test and methods of operating the probe systems are disclosed herein. The probe systems include an electromagnetically shielded enclosure, which defines an enclosed volume, and a temperature-controlled chuck, which defines a support surface configured to support a substrate that includes the DUT. The probe systems also include a probe assembly and an optical microscope. The probe systems further include an electromagnet and an electronically controlled positioning assembly. The electronically controlled positioning assembly includes a two-dimensional positioning stage, which is configured to selectively position a positioned assembly along a first two-dimensional positioning axis and also along a second two-dimensional positioning axis. The electronically controlled positioning assembly also includes a first one-dimensional positioning stage that operatively attaches the optical microscope to the positioned assembly and a second one-dimensional positioning stage that operatively attaches the electromagnet to the positioning assembly.

A chip testing method and apparatus, and an electronic equipment are provided. The method includes: determining, according to pad distribution information of a target chip, positions of set state pads and positions of non-set state pads in the target chip, the set state pads being pads with set states, and the set states including a first state or a second state; determining a plurality of pad state setting schemes according to the positions of the set state pads and the positions of the non-set state pads, the pad state setting schemes including setting each of the non-set state pads to the first state or the second state; and determining a test voltage setting scheme satisfying a preset condition according to information of differential voltage pad pairs in each of the pad state setting schemes, the differential voltage pad pair comprising two adjacent pads in different states.