A nuclear reaction detection device includes an FPGA (Field Programmable Gate Array) 100 which is arranged in an environment in which particle radiation is incident, and includes a user circuit 101 configured to output a value different from that in a normal state, if an SEU (Single Event Upset) occurs in a semiconductor element included in the FPGA, and an SEF detection unit 210 which detects that an abnormal operation (SEF) has occurred in the user circuit based on the output value from the user circuit 101 of the FPGA 100.

A production method for producing a circuit optimized to be protected against radiation includes a preliminary characterization stage performed on a reference circuit. The preliminary characterization stage includes the steps of: irradiating the reference circuit a plurality of times; after each irradiation, if one or more reference elements of the reference circuit have failed, locating said reference element(s); and mapping the impact of the irradiations on the reference surface of the reference circuit. The production method further includes an optimization stage comprising the step of adapting the position of at least one optimized radiation-sensitive element on at least one optimized surface of the optimized circuit as a function of the mapping performed on the reference circuit.

A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.

A signal transmission system with at least one signal encoder, a line, and a control and evaluation unit, wherein the signal encoder has an electronic unit and a power source, wherein the signal encoder feeds an imprinted current in the range between a preset first value and a preset second value into the line, in particular between 4 and 20 mA. The control and evaluation unit has a load and a microprocessor, and captures and evaluates a voltage that decreases via the load or a current that flows through the load. Additional information regarding the status of the components, can thus be captured and forwarded in a simple way, in that the load in the control and evaluation unit is connected in series to at least one electrical component at which a direct current appears when a current flows through the electrical component.

A testing system for evaluating the performance of an electrical/electronic UUT under dynamic operating conditions. The testing system includes a dynamic testing component (e.g., a centrifuge) for applying a stimulus to the UUT, and an iDAQ system configured to perform in situ data acquisition and real-time data analysis. The iDAQ system may also be subject to the stimulus. The iDAQ system includes a processor (e.g., an SoC) component, a power supply, a CR/I component, an IR component, and a single enclosure. The processor component may control the dynamic testing component, including varying in real-time the stimulus applied to the UUT. The processor component may include multiple input channels, and a high current/voltage subcomponent of the power supply may be configured to supply up to five hundred volts.

A method for predicting failure parameters of semiconductor devices can include receiving a set of data that includes (i) characteristics of a sample semiconductor device, and (ii) parameters characterizing a stress condition. The method further includes extracting a plurality of feature values from the set of data and inputting the plurality of feature values into a trained model executing on the one or more processors, wherein the trained model is configured according to an artificial intelligence (AI) algorithm based on a previous plurality of feature values, and wherein the trained model is operable to output a failure prediction based on the plurality of feature values. Further, the method includes generating, via the trained model, a predicted failure parameter of the sample semiconductor device due to the stress condition.

A testing system includes: an inspection module including a plurality of levels of inspection chambers in each of which a tester part having a tester configured to perform an electrical inspection of an inspection object and a probe card is accommodated; an aligner module configured to align the inspection object with the tester part; an alignment area in which the aligner module is accommodated; and a loader part configured to load the inspection object into the alignment area and unload the inspection object out of the aligner module, wherein the inspection module is located adjacent to the alignment area.

One preferable aspect of the present invention is a state detecting system which detects a state of a machine device based on a detection signal from a detecting element provided to the machine device, and is the state detecting system which includes a non-normal time rate detecting unit which detects a rate or a value as a non-normal time rate, the rate being a rate of an integration value of a time during which an amplitude of the detection signal exceeds a predetermined normal amplitude within a predetermined time, and the value being physically equivalent to the rate.

The disclosure relates to technology for determining stress on integrated circuits. These include using ring oscillators formed on the integrated circuit, where one ring oscillator has its frequency dependent on the current flowing through its stages being limited by its NMOS devices and another ring oscillator has its frequency dependent on the current flowing through its stages being limited by its PMOS devices. This allows the stress on the integrated circuit to be determined in different directions along the integrated circuit. A temperature sensor can be used to compensate for temperature dependence on the frequencies of the ring oscillators.

A probing system includes a chuck configured to support a device under test (DUT); a probe card disposed above the chuck and including a plurality of probes protruding from the probe card toward the chuck; and a platen disposed between the chuck and the probe card and configured to support the probe card, wherein the chuck includes a shielding member disposed between the platen and the chuck.