A system-on-chip includes a clock generation circuit configured to generate a reference clock of a first phase; a transmission circuit comprising a serializer configured to serialize data according to the reference clock of the first phase; a reception circuit comprising a clock data recovery (CDR) circuit configured to receive the serialized data and generate a first recovery clock and recovery data; and a Built In Self Test (BIST) circuit including a CDR performance monitoring circuit configured to generate a control signal provided to a delay controller configured to delay a clock signal by a preset phase difference, and the delay controller configured to delay the clock signal in response to the control signal by the preset phase difference and provide the delayed clock signal to the transmission circuit.

A method or system for estimating delays in design under tests (DUTs) using machine learning. The system accesses multiple DUTs, each comprising various logic blocks. For each DUT, a combinatorial path is identified, connecting one or more logic blocks. A feature vector is generated, including values of orthogonal features representing the combinatorial path's characteristics. Each DUT is compiled for emulation, and the delay of its combinatorial path is measured. These measured delays, along with the corresponding feature vectors, are used to train a machine learning delay model. The trained model is designed to receive a combinatorial path of a DUT as input and generate an estimated wire delay as output. This approach leverages machine learning to predict delays in electronic designs, improving the efficiency and accuracy of delay estimations in complex circuits.

An object of the present invention is to provide a semiconductor device, a semiconductor system, and a control method of a semiconductor device capable of accurately monitoring the lowest operating voltage of a circuit to be monitored. According to one embodiment, a monitor unit of a semiconductor system includes a voltage monitor that is driven by a second power supply voltage different from a first power supply voltage supplied to an internal circuit that is a circuit to be monitored and monitors the first power supply voltage, and a delay monitor that is driven by the first power supply voltage and monitors the signal propagation period of time of a critical path in the internal circuit.

Measurement of group delay for a device under test (DUT). A test signal includes (i) a low frequency sine wave f.sub.LF, (ii) sine wave harmonics at a high frequency f.sub.HF, (iii) L pairs of sideband components at frequencies k.Math.f.sub.HF2.Math.f.sub.LF, where k odd, and M pairs of sideband components at frequencies k.Math.f.sub.HFf.sub.LF, where k is even. At DUT output, (i) phase .sub.LF at frequency f.sub.LF is measured, (ii) both sideband phase .sub.right(k) at frequencies k.Math.f.sub.HF+2.Math.f.sub.LF and phase .sub.left(k) at frequencies k.Math.f.sub.HF2.Math.f.sub.LF for odd k, are measured, and (iii) both sideband phases .sub.right(k) at frequencies k.Math.f.sub.HF+f.sub.LF and .sub.left(k) at frequencies k.Math.f.sub.HFf.sub.LF for even k, are measured. Group delay .sub.k at frequencies k.Math.F.sub.HF, are determined from: .sub.k=(.sub.right(k).sub.left(k)4.Math..sub.L)/(4.Math.f.sub.LF) for k odd, and .sub.k=(.sub.right(k).sub.left(k)2.Math..sub.L)/(2.Math.f.sub.LF) for k even.

Measurement of group delay for a device under test (DUT). A test signal includes (i) a low frequency sine wave f.sub.LF, (ii) sine wave harmonics at a high frequency f.sub.HF, (iii) L pairs of sideband components at frequencies k.Math.f.sub.HF2.Math.f.sub.LF, where k odd, and M pairs of sideband components at frequencies k.Math.f.sub.HFf.sub.LF, where k is even. At DUT output, (i) phase .sub.LF at frequency f.sub.LF is measured, (ii) both sideband phase .sub.right(k) at frequencies k.Math.f.sub.HF+2.Math.f.sub.LF and phase .sub.left(k) at frequencies k.Math.f.sub.HF2.Math.f.sub.LF for odd k, are measured, and (iii) both sideband phases .sub.right(k) at frequencies k.Math.f.sub.HF+f.sub.LF and .sub.left(k) at frequencies k.Math.f.sub.HFf.sub.LF for even k, are measured. Group delay .sub.k at frequencies k.Math.F.sub.HF, are determined from: .sub.k=(.sub.right(k).sub.left(k)4.Math..sub.L)/(4.Math.f.sub.LF) for k odd, and .sub.k=(.sub.right(k).sub.left(k)2.Math..sub.L)/(2.Math.f.sub.LF) for k even.

Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

A method for implementing a programmable critical delay path measurement in-line with the critical path logic cells. Additionally, the delay measurement creates a code to be used with a programmable DLL which indicates the delay of the measured critical path. This code can also be used by an off line First Fail Circuit which can mimic the delay of the critical path and give an indication of the critical path delay. The target of this invention is to create a method to optimize the required operating voltage of an integrated circuit per specific speed requirement, overcoming different process variations, temperatures changes and in die variations.

A delay measurement system and a measurement method are provided. The delay measurement system includes a delay control device and a comparator. The delay control device is configured to generate a second signal in response to a first signal, wherein a rising edge of the second signal delays a first delay time with respect to a rising edge of the first signal, and the first delay time is controlled in response to an output signal of a comparator. The comparator is configured to compare the first delay time with a second delay time and output the output signal, wherein a rising edge of a third signal delays the second delay time with respect to the rising edge of the first signal, and the third signal is generated by a device under test (DUT) in response to the first signal.

A delay measurement system and a measurement method are provided. The delay measurement system includes a delay control device and a comparator. The delay control device is configured to generate a second signal in response to a first signal, wherein a rising edge of the second signal delays a first delay time with respect to a rising edge of the first signal, and the first delay time is controlled in response to an output signal of a comparator. The comparator is configured to compare the first delay time with a second delay time and output the output signal, wherein a rising edge of a third signal delays the second delay time with respect to the rising edge of the first signal, and the third signal is generated by a device under test (DUT) in response to the first signal.

A measurement circuit and method is provided for generating an oscillating output signal used to derive timing information. The measurement circuit includes a ring oscillator having a plurality of unit cells, where each unit cell comprises at least a storage element whose output signal is used to determine a clock input signal for an adjacent unit cell within the ring oscillator. Control circuitry performs a control operation to control either a set function or a reset function of the storage element in each of the unit cells, in dependence on set or reset signals input to the control circuitry. Oscillation initiation circuitry is used to assert a clock input signal to the storage element in a first unit cell in order to initiate generation of the oscillating output signal, and the control circuitry then performs the control operation in order to control a value of the output signal of the storage element in each unit cell so as to cause the oscillating output signal to be maintained. Such an approach provides a particularly simple and efficient mechanism for deriving timing information for various circuit blocks that include a storage element.