A testing method is performed by at least one processor and includes following operations: converting first data associated with a scan test into a program, in which the program is configured to observe an untested part of a circuitry that is unable to be tested in the scan test; performing circuit simulations with the program according to a netlist file indicating the circuitry and testing patterns, in order to rank the testing patterns to generate second data; selecting at least one candidate testing pattern from the testing patterns according to the second data; and performing at least one fault simulation on the circuitry according to the netlist file and the at least one candidate testing pattern, in order to test the circuitry.

A cell-aware defect characterization method includes partitioning a multibit cell netlist file into multiple single-bit partition netlist files, and then generating a cell-aware test model for each partition netlist file. Partitioning is performed such that each partition netlist file includes a corresponding flip-flop along with input, output and control pins that are operably coupled to the input, output and control terminals of the corresponding flip-flop, and all active, passive and parasitic circuit elements that are coupled in the signal paths extending between the corresponding flip-flop and the input/output/control pins. Shared resources (e.g., clock or scan select pins and associated signal lines) that are utilized by two or more flip-flops are included in each associated partition. The partitioning process is performed using either a structural back-tracing approach or a logic simulation approach.

A method, system, and architecture (100) for adaptively field testing for hardware faults on an integrated circuit device includes a central quality assurance server (121) which receives specified hardware metric data (131) monitored at an integrated circuit device (110) in the field, identifies prioritized built-in self-test (BIST) fault detection tests (134) based on the specified hardware metric data, securely downloads the prioritized BIST fault detection tests (132) to the integrated circuit device for execution to identify a first hardware fault at the integrated circuit device, and then receives diagnosis information (133) identifying the first hardware fault from the integrated circuit device which is used to update the prioritized BIST fault detection tests.

The Translation Layer is embedded into each circuit under test (CUT) to modularize test process. The modularized tests are self-contained and performed in isolation. They are composed without consideration of environment constraints. The CUT and its environment constraints can be concurrently be tested in isolation and independently. Interconnections between the CUT and the environment can be tested in the environment constraint test without additional dedicated test logic. The modularized test process allows the test patterns of the environment constraints to be derived from those of the CUT. The resulting test patterns are used to compose the test patterns of a target system. Since the test process is recursive in nature, the modularized test of each constituent subsystem or design core can be performed in isolation in the target system, while the environment constraints and the interconnections are being tested concurrently.

This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

A first circuit design and a second circuit design are analyzed to determine part of the second circuit design structurally similar to part of the first circuit design. A first set of test patterns for the first circuit design is modified to generate a second set of test patterns for the second circuit design by reusing values of bits in the first set of test patterns associated with the part of the first circuit design as values of bits in the second set of test patterns associated with the part of the second circuit design. Fault simulation is performed on the second circuit design using the second set of test patterns to determine a subset of faults undetectable by the second set of test patterns. Test pattern generation is performed for the subset of faults to generate a third set of test patterns for the second circuit design.

A method, system, and architecture (100) for adaptively field testing for hardware faults on an integrated circuit device includes a central quality assurance server (121) which receives specified hardware metric data (131) monitored at an integrated circuit device (110) in the field, identifies prioritized built-in self-test (BIST) fault detection tests (134) based on the specified hardware metric data, securely downloads the prioritized BIST fault detection tests (132) to the integrated circuit device for execution to identify a first hardware fault at the integrated circuit device, and then receives diagnosis information (133) identifying the first hardware fault from the integrated circuit device which is used to update the prioritized BIST fault detection tests.

This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

A system and method for testing a device under test (DUT) combines measurement data of field components values made at different sampling locations away from the DUT with computer-aided design layout of the DUT. The combined computer-aided design layout of the DUT and the measurement data can then be displayed for analysis.

Methods and apparatus are described for converting a pre-silicon Open Verification Methodology or Universal Verification Methodology (OVM/UVM) device under test (DUT) into a design implementable on a programmable integrated circuit (IC) and for converting the pre-silicon OVM/UVM stimulus from the driver and expected response from the scoreboard into timing aware stimulus-response vectors that can be applied through the tester onto the pads of the programmable IC that contains the implemented design. This approach can handle the clock and other input stimuli changing concurrently in the pre-silicon testbench, and the vectors generated therefrom will be in the proper form so as to work deterministically on the silicon on the tester.