An integrated circuit (IC) with a TSV test circuit, a TSV test method are provided, pertaining to IC technologies. The IC may include a first TSV, a second TSV and a phase detector. A first end of the first TSV may be coupled to a predetermined signal output, and a second end of the first TSV may be coupled to a first end of the second TSV. A second end of the second TSV may be coupled to a first input of the phase detector, and a second input of the phase detector may be coupled to the predetermined signal output. The phase detector may be configured to determine a phase difference between signals at the first and the second inputs. In this IC, a defective TSV can be identified and segregated with a redundant TSV. This IC facilitates efficient fault correction and signal routing in the IC.

In one embodiment, an apparatus includes multiple die and at least one interconnect to couple the die. A first die includes one or more cores, a first fabric and a first fabric transactor coupled to the first fabric, the first fabric transactor to initiate a functional test of the apparatus in response to a test signal, cause at least one first test transaction to be sent to a second die, receive a first response to the at least one first test transaction from the second die, and identify, based at least in part on the first response to the at least one test transaction, a location of a failure and report the location of the failure to a destination. Other embodiments are described and claimed.

A semiconductor or integrated circuit block including a sense node and a converter circuit, in which the sense node develops a low frequency electrical parameter that is constant or varies at a frequency below a predetermined frequency level, and in which the converter circuit converts the low frequency electrical parameter into an alternating electrical parameter having a frequency at or above the predetermined frequency level sufficient to modulate a laser beam focused within a laser probe area of the converter circuit. The converter may include a ring oscillator, a switch circuit controlled by a clock enable signal, a capacitor having a charge rate based on the low frequency electrical parameter, etc. The laser probe area has a frequency level based on a level of the low frequency electrical parameter to modulate the reflected laser beam for measurement of the electrical parameter by a laser voltage probe test system.

This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.

An integrated circuit (IC) with a TSV test circuit, a TSV test method are provided, pertaining to IC technologies. The IC may include a first TSV, a second TSV and a phase detector. A first end of the first TSV may be coupled to a predetermined signal output, and a second end of the first TSV may be coupled to a first end of the second TSV. A second end of the second TSV may be coupled to a first input of the phase detector, and a second input of the phase detector may be coupled to the predetermined signal output. The phase detector may be configured to determine a phase difference between signals at the first and the second inputs. In this IC, a defective TSV can be identified and segregated with a redundant TSV. This IC facilitates efficient fault correction and signal routing in the IC.

This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.

A method of in-system structural testing of a system-on-chip (SoC) using a peripheral interface port is described. The method including enabling a scan interface controller of the SoC through the peripheral interface port. The method also includes streaming structural test patterns in the SoC through the scan interface controller.

An integrated circuit comprising: a plurality of on-chip-instrument-modules; a test-controller-module configured to communicate data with the plurality of on-chip-instrument-modules; a functional-module configured to communicate data with the plurality of on-chip-instrument-modules; and an on-chip-instrument-controller. The on-chip-instrument controller is configured to: for each of the plurality of on-chip-instrument-modules, store an access-indicator; and based on a value of the access-indicator for each on-chip-instrument-module, enable the on-chip-instrument-module to communicate with either: the test-controller-module; or the functional-module.

An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.

Embodiments herein describe techniques for binning integrated circuits (ICs) using an adaptive binning system that can re-bin the ICs in response to receiving a new or updated test specification. Unlike static binning systems, in one embodiment, the binning system receives measured test data from a testing system. Put differently, instead of a testing apparatus simply indicating whether an IC does (or does not) satisfy the criteria in the test specification, the testing apparatus provides measured test data to the binning system. The binning apparatus can then store the received test data. As such, if a new test specification is received or generated, the binning system can use the already saved test data to re-bin the ICs using the criteria in the new test specification without having to re-test the ICs. In this manner, the binning system can re-categorize the ICs as customer needs or customer demand changes.