Examples described herein provide a method for evaluating a programmable logic device (PLD) for compatibility with user designs. The method includes using a processor-based system: obtaining an indication of one or more failure bits of configuration memory of a programmable logic device (PLD); determining whether each of the one or more failure bits corresponds to a configuration memory bit to be used by a first PLD user design; if any of the one or more failure bits corresponds to a configuration memory bit to be used by the first PLD user design, classifying the PLD as unusable for the first PLD user design; and if none of the one or more failure bits corresponds to a configuration memory bit to be used by the first PLD user design, classifying the PLD as usable for the first PLD user design.

A field programmable gate array (FPGA) for improving the reliability of a key configuration bitstream by reusing a buffer memory includes a configuration buffer, a configuration memory and a control circuit. The configuration memory includes N configuration blocks. The FPGA stores a key configuration chain by using the configuration buffer and ensures correct content of the key configuration chain through an error correcting code (ECC) check function of the configuration buffer, so that when the FPGA runs normally, a control circuit reads the key configuration chain in the configuration buffer at an interval of a predetermined time and writes the key configuration chain into a corresponding configuration block to update the key configuration chain, thereby ensuring accuracy of the content of the key configuration chain and improving running reliability of the FPGA.

An electronic controller includes: a logic circuit that is reconfigurable based on a reconfiguration instruction; an arithmetic unit that is configured in the logic circuit; a processing controller that transmits the reconfiguration instruction of the arithmetic unit to the logic circuit and that makes the reconfigured arithmetic unit execute predetermined operation; and a testing unit that executes an operation test for an arithmetic unit when the arithmetic unit is reconfigured, and that transmits the result of the operation test to the processing controller as a notice. Here, the processing controller makes the arithmetic unit execute predetermined processing based on the notice received from the testing unit.

A programmable integrated circuit may include logic, signal select hardware, programmable signal analysis hardware, an embedded microcontroller, and a hardware interface. The logic performs one or more functions and outputs a plurality of signals. The signal select hardware selects one or more of the signals output from the logic. The programmable signal analysis hardware analyzes the selected signals to produce diagnostic data. The embedded microcontroller receives the diagnostic data from the programmable signal analysis hardware and may reconfigure the logic based on the diagnostic data. The hardware interface connects the programmable signal analysis hardware and the embedded microcontroller to transport the diagnostic data.

An arithmetic operation device executes a test using a partially reconfigurable programmable logic unit, the programmable logic unit includes a test target circuit which is a user circuit, and a non-test circuit which is a user circuit which is not the test target circuit, and the arithmetic operation device includes a configuration control unit which causes the programmable logic unit to form, by partial reconfiguration, a test partition unit which separates the test target circuit and the non-test circuit, and a partition control unit which controls the test partition unit to test the test target circuit.

A programmable integrated circuit may include logic, signal select hardware, programmable signal analysis hardware, an embedded microcontroller, and a hardware interface. The logic performs one or more functions and outputs a plurality of signals. The signal select hardware selects one or more of the signals output from the logic. The programmable signal analysis hardware analyzes the selected signals to produce diagnostic data. The embedded microcontroller receives the diagnostic data from the programmable signal analysis hardware and may reconfigure the logic based on the diagnostic data. The hardware interface connects the programmable signal analysis hardware and the embedded microcontroller to transport the diagnostic data.

The present disclosure relates to a circuit board that includes a first edge connector configured to communicatively couple the circuit board to a first connector of a second circuit board. The first edge connector extends from a side of the circuit board a first length. The circuit board also includes a second edge connector configured to communicatively couple the circuit board to a second connector of the second circuit board. The second edge connector extends from the side of the circuit board a second length that is different than the first length.

Systems and methods for monitoring a number of operating conditions of a programmable device are disclosed. In some implementations, the system may include a root monitor including circuitry configured to generate a reference voltage, a plurality of sensors and satellite monitors distributed across the programmable device, and a interconnect system coupled to the root monitor and to each of the plurality of satellite monitors. Each of the satellite monitors may be in a vicinity of and coupled to a corresponding one of the plurality of sensors via a local interconnect. The interconnect system may include one or more analog channels configured to distribute the reference voltage to each of the plurality of satellite monitors, and may include one or more digital channels configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor as data packets.

Systems and methods for monitoring operating conditions of a programmable device are disclosed. The system may include a root monitor configured to generate a reference voltage, a plurality of sensors distributed across the device, and a plurality of satellite monitors distributed across the device. Each of the satellite monitors may be coupled to a corresponding sensor via a local interconnect, and may be configured to convert analog signals generated by the sensor into digital data indicative of one or more operating conditions of an associated circuit. In some implementations, each satellite monitor may include a circuit to store a local reference voltage, an analog-to-digital converter (ADC) to convert the analog signals into digital codes, a calibration circuit to generate a correction factor indicative of errors in the digital codes, and a correction circuit to correct the digital codes based on the correction factor.

A scan chain latch circuit, a method of operating a latch circuit in a scan chain, and a computer-readable medium having stored thereon a data structure defining a scan chain latch circuit for instantiation on a semiconductor die are disclosed. In an embodiment, the scan chain latch circuit comprises a first latch for holding one data value, a second latch for holding another data value, and a multiplexor. The one data value is applied to a first data input of the multiplexor and the another data value is applied to a second data input of the multiplexor. An alternating clock signal is applied to a select input of the multiplexor to control the output of the multiplexor, wherein the output of the multiplexor toggles between the two data values held in the two latches at a defined frequency.