Methods and apparatus for self test of safety logic in safety critical devices is provided in which the safety logic includes comparator logic coupled to a circuit under test (CUT) in a safety critical device and the self test logic is configured to test the comparator logic. The self test logic may be implemented as a single cycle parallel bit inversion approach, a multi-cycle serial bit inversion approach, or a single cycle test pattern injection approach.

Various examples of methods and systems are disclosed for correction of phase and amplitude errors that occur in transmission lines connecting transmitter/receiver devices to measurement fixtures. In one example, a method is described that includes using time domain processing to determine a phase shift from the measurement fixture that can occur between calibration measurements and measurements of the specimen under test. In another example, a method is described that includes frequency-domain processing of the signals to obtain both phase and amplitude corrections. Including these phase and amplitude corrections in the calibration procedure can reduce or minimize the errors induced in the measurements when the transmission line(s) experience either temperature changes or physical deflections, among other things.

Various examples of methods and systems are disclosed for correction of phase and amplitude errors that occur in transmission lines connecting transmitter/receiver devices to measurement fixtures. In one example, a method is described that includes using time domain processing to determine a phase shift from the measurement fixture that can occur between calibration measurements and measurements of the specimen under test. In another example, a method is described that includes frequency-domain processing of the signals to obtain both phase and amplitude corrections. Including these phase and amplitude corrections in the calibration procedure can reduce or minimize the errors induced in the measurements when the transmission line(s) experience either temperature changes or physical deflections, among other things.

Embodiments of the present disclosure relate to a method and an apparatus of analyzing data, and a storage medium. The method of analyzing data includes: obtaining a single shmoo plot of each pin of a memory particle; and constructing an integrated shmoo plot of the memory particle based on the single shmoo plot of each of the pins, wherein each test point of the integrated shmoo plot is marked with a pass proportion, and the pass proportion is configured to represent a proportion of a quantity of passed single shmoo plots at a corresponding test point to a total quantity of the single shmoo plots.

System analysis by receiving a model of a complex system design. The model includes at least one layer. The analysis includes performing a plurality of simulations of the performance of the layer. The number of simulations is determined according to a number of system components associated with the layer. The analysis further includes determining a worst-case result for a set of simulations from the plurality of simulations and assigning the worst-case result to an overall system simulation.

Presented embodiments facilitate efficient and effective diagnostic of test system operations, including temperature control of test equipment components. In one embodiment a test equipment diagnostic method includes applying a known/expected first bit pattern to a test equipment component, applying a known/expected second bit pattern to a test equipment component, and performing a test equipment temperature control analysis based upon the results of applying the known/expected first bit pattern and known/expected second bit pattern. The first bit pattern and second bit pattern have known/expected respective thermal loads and corresponding respective first known/expected/expected temperature and second known/expected/expected temperature. In one embodiment, performing a test equipment temperature control analysis includes determining if temperature control components control a temperature of the test equipment component within acceptable tolerances. In one exemplary implementation, the test equipment component is a test control component (e.g., a field programmable gate array (FPGA), etc.).

Embodiments of the present disclosure pertain to techniques for generating and/or verification of integrated circuits. In one embodiment, parameters of a circuit to be generated are used to automatically generate customized test programs. In another embodiment, an integrated circuit comprises circuits to facilitate testing and controlling test coverage. In yet another embodiment, data obtained from physical circuits is used to generated or modify customized predefined behavioral models of functional circuit components having particular parameters.

Presented embodiments facilitate efficient and effective diagnostic of test system operations, including temperature control of test equipment components. In one embodiment a test equipment diagnostic method includes applying a known/expected first bit pattern to a test equipment component, applying a known/expected second bit pattern to a test equipment component, and performing a test equipment temperature control analysis based upon the results of applying the known/expected first bit pattern and known/expected second bit pattern. The first bit pattern and second bit pattern have known/expected respective thermal loads and corresponding respective first known/expected/expected temperature and second known/expected/expected temperature. In one embodiment, performing a test equipment temperature control analysis includes determining if temperature control components control a temperature of the test equipment component within acceptable tolerances. In one exemplary implementation, the test equipment component is a test control component (e.g., a field programmable gate array (FPGA), etc.).

A method of identifying error patterns during automated device testing comprises receiving a data pattern from a plurality of capture modules programmed on a programmable logic device, wherein the plurality of capture modules are programmable and operable to selectively capture data traffic to be monitored, and wherein the data traffic comprises a flow of traffic between a DUT and the programmable logic device. The method further comprises comparing the data pattern with known signatures in an error signature database. Also, the method comprises correlating the data pattern with one or more matching known signatures in the error signature database and assigning a score to each of the one or more matching known signatures in the error signature database based a level of correlation.

Methods and apparatus for self test of safety logic in safety critical devices is provided in which the safety logic includes comparator logic coupled to a circuit under test (CUT) in a safety critical device and the self test logic is configured to test the comparator logic. The self test logic may be implemented as a single cycle parallel bit inversion approach, a multi-cycle serial bit inversion approach, or a single cycle test pattern injection approach.