Monolithic three-dimensional integration can achieve higher device density compared to 3D integration using through-silicon vias. A test solution for M3D integrated circuits (ICs) is based on dedicated test layers inserted between functional layers. A structure includes a first functional layer having first functional components of the IC with first test scan chains and a second functional layer having second functional components of the IC with second test scan chains. A dedicated test layer is located between the first functional layer and the second functional layer. The test layer includes an interface register controlling signals from a testing module to one of the first test scan chains and the second test scan chains, and an instruction register connected to the interface register. The instruction register processes testing instructions from the testing module. Inter-layer vias connect the first functional components, the second functional components, and the testing module through the test layer.

A test apparatus includes a first insulation housing, a second insulation housing configured to be coupled to the first insulation housing, and a test board including a first portion and a second portion. The first insulation housing and the second insulation housing are configured to cover the first portion of the test board and to expose the second portion of the test board.

An integrated circuit test apparatus includes: a first test unit configured to output a current for a built-in self test (BIST) progress state for each internal circuit of an integrated circuit in a BIST test mode and to determine whether each internal circuit operates normally in a wake-up mode of the integrated circuit; and a first determination module configured to determine whether each internal circuit is in a stuck state based on a change detected by the first test unit.

Some embodiments are directed to a test apparatus for testing a device. The apparatus includes a test device having a memory for storing data processing instructions and processors configured, when the data processing instructions are executed, to execute test code in order to implement a test operation on the device being tested. The test code defines test patterns and test algorithms to be applied to instruments for testing the device being tested, and is in a first format that is independent of the test interface between the test device and the device being tested. The apparatus also includes an interface controller coupled to the device being tested and configured to convert communications generated by the test device during the execution of the test code into a second format suitable for the test interface, and to convert communications from the device being tested into the first format.

A method, computer system, and computer program product are provided for stress-testing electronics using telemetry modeling. Telemetry data is received from one or more devices under test during a hardware testing phase, the telemetry data including one or more telemetry parameters. The telemetry data is processed using a predictive model to determine future values for the one or more telemetry parameters. Additional hardware testing is performed, wherein the additional hardware testing includes adjusting one or more testing components based on the determined future values.

A system for data creation, storage, analysis, and training while margin testing includes a margin test generator coupled through an interface to a Device Under Test (DUT). The margin test generator is structured to modify test signals for testing the DUT during one or more testing states of a test session to create testing results. The testing results are stored in a data repository along with a DUT identifier of the DUT tested during the test session. A comparator determine whether any results of the DUT test results match a predictive outcome that is based from an analysis of previous DUT tests. If so, a message generator produces an indication that the tested DUT matched the predictive outcome.

An electronic test apparatus is adapted for testing an electronic component which includes a circuit substrate and a plurality of contact electrodes disposed on the circuit substrate. The electronic test apparatus includes a test seat and a plurality of spring probes. The test seat includes a metallic main body that has a first side adapted to be in contact with the circuit substrate and a second side opposite to the first side, and that is formed with a plurality of spaced-apart probe holes extending through the first and second sides, and a temperature sensor disposed in the metallic main body. The spring probes are adapted to be electrically connected to the contact electrodes and each is positioned in a respective one of the probe holes.

A test apparatus includes a first insulation housing, a second insulation housing configured to be coupled to the first insulation housing, and a test board including a first portion and a second portion. The first insulation housing and the second insulation housing are configured to cover the first portion of the test board and to expose the second portion of the test board.

Provided is a technique related to a terminal apparatus, a base station apparatus, a communication system, a communication method, and an integrated circuit that are capable of efficiently performing device-to-device communication. In a case where a terminal apparatus capable of direct communication between terminal apparatuses starts a timer corresponding to a group index that identifies short-range group communication, to which the terminal apparatus belongs, and the timer expires, switching is performed from a first radio resource allocation method, by which a radio resource to be used for the direct communication is requested to a base station apparatus, to a second radio resource allocation method by which the terminal apparatus selects a radio resource to be used for the direct communication.

A measurement system for testing a device under test is described, with at least two antennas, at least two reflectors, a signal generation and/or analysis equipment and a test location. Each of the antennas is assigned to a corresponding reflector. Each of the antennas is configured to transmit/receive an electromagnetic signal so that a beam path is provided between the respective antenna and the test location. The electromagnetic signal is reflected by the respective reflector so that the electromagnetic signal corresponds to a planar wave. The beam paths have different angular orientations that are adjustable. At least one antenna and the corresponding reflector are coupled with each other so that an integrated beam path adjustment unit is established including at least one antenna and the corresponding reflector. Further, a testing method is described.