A test and measurement management device, including a request queue to receive a request from a request module, the request including an identification of a device under test and a requested measurement and one or more processors. The one or more processors are configured to receive the request from the request queue, generate a command to instruct an optical switch to select a port associated with the device under test based on the identification of the device under test, determine the requested measurement from the request, and based on the requested measurement and the identification of the device under test, generate instructions to configure a test and measurement instrument to perform the requested measurement.

A method for operating a data processing system to compute the response of a DUT to a modulated input signal is disclosed. The method includes determining a set of parameters for a first model of the DUT from a plurality of measurements of output values from the DUT, each output value includes a measurement of a gain and phase shift provided by the DUT when the DUT is stimulated with a single tone input signal having a frequency in a frequency range determined by the modulated signal. The method also determines a second model that characterizes noise generated by the DUT at the single tone input signals. A performance parameter for an output signal that would be obtained by applying the modulated input signal to an input of the DUT, and receiving the output of the DUT is then determined from the first and second models.

An electronic test apparatus is adapted for testing an electronic component which includes a circuit substrate and a plurality of contact electrodes disposed on the circuit substrate. The electronic test apparatus includes a test seat and a plurality of spring probes. The test seat includes a metallic main body that has a first side adapted to be in contact with the circuit substrate and a second side opposite to the first side, and that is formed with a plurality of spaced-apart probe holes extending through the first and second sides, and a temperature sensor disposed in the metallic main body. The spring probes are adapted to be electrically connected to the contact electrodes and each is positioned in a respective one of the probe holes.

An automated test equipment (ATE) apparatus is presented. The apparatus comprises a computer system comprising a system controller, wherein the system controller is communicatively coupled to a site module board comprising a tester processor and an FPGA wherein the system controller is operable to transmit instructions to the tester processor, and wherein the tester processor is operable to generate commands and data from the instructions for coordinating testing of a device under test (DUT) wherein the site module board comprises a compact form factor suitable for use during prototyping, and wherein the site module board is operable to be coupled with a DUT. Further, the FPGA is communicatively coupled to the tester processor, wherein the FPGA comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing the DUT.

Embodiments are directed to a semiconductor wafer having on-wafer circuitry. The on-wafer circuitry includes functional circuitry and first drive circuitry communicatively coupled to the functional circuitry. The on-wafer circuitry further includes test-only circuitry communicatively coupled to the functional circuitry, along with second drive circuitry communicatively coupled to the test-only circuitry. The control circuitry is communicatively coupled to the second drive circuitry and the test-only circuitry, wherein the first drive circuitry is configured to drive the functional circuitry in a first manner, and wherein the control circuitry is configured to control the second drive circuitry to drive the test-only circuitry in a second manner that is independent of the first manner.

Embodiments provide a scheduler for scheduling test times of a plurality of tester software environments for an automatic test equipment. The scheduler is configured to automatically assign test times to the plurality of tester software environments, to acquire test instructions from a tester software environment of the plurality of tester software environments to which a current test time is assigned, to control the automatic test equipment to perform a test according to the test instructions in order to obtain test results, and to provide the test results to the tester software environment of the plurality of tester software environments to which the current test time is assigned.

Monolithic three-dimensional integration can achieve higher device density compared to 3D integration using through-silicon vias. A test solution for M3D integrated circuits (ICs) is based on dedicated test layers inserted between functional layers. A structure includes a first functional layer having first functional components of the IC with first test scan chains and a second functional layer having second functional components of the IC with second test scan chains. A dedicated test layer is located between the first functional layer and the second functional layer. The test layer includes an interface register controlling signals from a testing module to one of the first test scan chains and the second test scan chains, and an instruction register connected to the interface register. The instruction register processes testing instructions from the testing module. Inter-layer vias connect the first functional components, the second functional components, and the testing module through the test layer.

An automated test equipment for testing a device under test includes a control unit and a plurality of tester subunits. The control unit is configured to put the tester subunits in a state of lower activity in dependence on a current demand on the test resources.

A method, computer system, and computer program product are provided for stress-testing electronics using telemetry modeling. Telemetry data is received from one or more devices under test during a hardware testing phase, the telemetry data including one or more telemetry parameters. The telemetry data is processed using a predictive model to determine future values for the one or more telemetry parameters. Additional hardware testing is performed, wherein the additional hardware testing includes adjusting one or more testing components based on the determined future values.

The invention concerns a test program executor for an Automated Test Equipment, wherein the test program executor is configured to execute a test flow having a plurality of test suites, wherein the test program executor is configured to asynchronously execute the plurality of test suites, wherein a test suite contains a call of a function of a subsystem, wherein the function of the subsystem is related with a subsystem operation that is to be executed by the subsystem, and to signal a call of a function of a subsystem by transmitting an asynchronous request to the subsystem, the asynchronous request having a call-specific call tree hierarchy address and the call-specific operation to be executed by the subsystem, and wherein the test program executor is further configured to determine an execution order of the subsystem operations, such that the execution order of the subsystem operations depends on their call-specific call tree hierarchy addresses.