The present disclosure generally relates to an embedded physical layer (EPHY) for a field programmable gate array (FPGA). The EPHY for the FPGA is for a testing device that can receive and transmit in both the high speed PHYs, as well as low speed PHYs, such as MIPI PHYs (MPHYs), to meet universal flash storage (UFS) specifications. The testing device with the EPHY for the FPGA provides flexibility to support any specification updates without the need of application specific (ASIC) production cycles.

Techniques include configuring a sequential circuit monitor having been generated by applying a quantifier elimination to each random bit position of random inputs associated with a formal verification driver and selecting a value for random inputs to drive a next stage logic of sequential circuit simulation monitor, a state of the next stage logic being used by sequential circuit simulation monitor to generate sequential inputs to match those permitted by formal verification driver, formal verification driver being specified for a DUT input interface. An equivalence check between sequential circuit simulation monitor and original formal driver matches the same set of sequential inputs permitted original formal driver. The sequential circuit simulation monitor is coupled to a simulation environment and the DUT in simulation environment, sequential circuit simulation monitor being configured to flag an input sequence from the simulation environment not permitted by formal verification driver based on the sequential inputs.

Systems, methods, and computer program products for virtual machine testing of an electric machine (8). A test signature including parameter values measured during one or more static tests of the electric machine (8) is compared to a reference signature generated by performing a similar series of static tests on a reference machine (42). The reference machine (42) is then validated by subjecting the reference machine to full-load dynamic testing. The test and reference signatures may include a plurality of parameters each characterizing a physical property of the respective machines (8, 42) in one or more physical domains The parameters are selected so that the electric machine (8) can be qualified for operation in the field by comparing the test signature to the reference signature, thereby avoiding the need for full-load dynamic testing of the electric machine (8).

A battery emulation apparatus for supplying a device-under-test (DUT) with electrical power, comprising output terminals for connecting the DUT and an output voltage module providing a variable DC output voltage. A user interface receives a user input comprising the setting of battery parameter(s) and measurement criteria. A data storage stores data representing battery models. A processor selects a battery model based on the parameter(s) and controls the output voltage module to emulate characteristics of the selected battery model(s) according the data, while supplying the DUT with the output voltage. The processor monitors a response of the DUT and/or the output voltage module to the emulated characteristics of the selected battery model(s), wherein the response comprises a physical measurement value. The processor evaluates said physical measurement value based on the set measurement criteria in order to assess the suitability of the selected model(s).

Provided is a test apparatus including an optical test signal generating section that generates an optical test signal; an optical signal supplying section that supplies the optical test signal to a device under test that is a testing target among a plurality of the devices under test; a first optical switch section that selects, from among optical signals output by the plurality of devices under test, the optical signal output by the device under test that is the testing target; and an optical signal receiving section that receives the selected optical signal.

The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device. According to the present disclosure, messages are modulated over DC voltages applied to the power terminals of a device to input test/debug messages to the device and output test/debug messages from the device. The present disclosure advantageously allows a device to be tested and/or debugged without the device having any shared or dedicated test or debug interface terminals.

A method for operating a test apparatus including a plurality of shared resources is shown, wherein the plurality of shared resources can be used in different instruments. The method includes blocking a first set of resource blockers when a first instrument, which requires a first subset of the shared resources, is to be executed. Furthermore, the method tries to block a second set of resource blockers, when a second instrument, which requires a second subset of the shared resources, is to be executed. Therefore, the first set of resource blockers is different from the second set of resource blockers and a plurality of resource blockers are assigned to a shared resource, which is involved in a conflicting combination of instruments and in a non-conflicting combination of instruments.

Methods of producing augmented probe system images and associated probe systems. A method of producing an augmented probe system image includes recording a base probe system image, generating the augmented probe system image at least partially based on the base probe system image, and presenting the augmented probe system image. The augmented probe system image includes a representation of at least a portion of the probe system that is obscured in the base probe system image. In some examples, a probe system includes a chuck, a probe assembly, an imaging device, and a controller programmed to perform methods disclosed herein.

Techniques include configuring a sequential circuit monitor having been generated by applying a quantifier elimination to each random bit position of random inputs associated with a formal verification driver and selecting a value for random inputs to drive a next stage logic of sequential circuit simulation monitor, a state of the next stage logic being used by sequential circuit simulation monitor to generate sequential inputs to match those permitted by formal verification driver, formal verification driver being specified for a DUT input interface. An equivalence check between sequential circuit simulation monitor and original formal driver matches the same set of sequential inputs permitted original formal driver. The sequential circuit simulation monitor is coupled to a simulation environment and the DUT in simulation environment, sequential circuit simulation monitor being configured to flag an input sequence from the simulation environment not permitted by formal verification driver based on the sequential inputs.

A pulsed-laser LADA system is provided, which utilizes temporal resolution to enhance spatial resolution. The system is capable of resolving CMOS pairs within the illumination spot using synchronization of laser pulses with the DUT clock. The system can be implemented using laser wavelength having photon energy above the silicon bandgap so as to perform single-photon LADA or wavelength having photon energy below the silicon bandgap so as to generate two-photon LADA. The timing of the laser pulses can be adjusted using two feedback loops tied to the clock signal of an ATE, or by adjusting the ATE's clock signal with reference to a fixed-pulse laser source.