The present invention relates to a self diagnostic apparatus for an electronic device, which includes a vector memory configured to store a test function code for testing a device under test (DUT) equipped with a plurality of cores which perform arithmetic operations, a function test expected value corresponding to a function test according to the test function code, a design for test (DFT) test code, a DFT test expected value corresponding to a DFT test according to the DFT test code, and a non-test function code for a general arithmetic operation or an operation of the DUT; a test data storage configured to store test data including a DFT test code result value which is a result of the DFT test according to the DFT test code, a test function code result value which is a result of the function test according to the test function code, and a non-test function code result value which is a result of the function test according to the non-test function code; and a safety region test controller configured to select one among the test function code, the DFT test code, and the non-test function code to select a test mode, control an environmental variable of a test signal applied to the DUT in response to the selected test mode and test the DUT, compare the function test expected value stored in the vector memory with the test function code result value stored in the test data storage, and compare the DFT test expected value stored in the vector memory with the DFT test code result value stored in the test data storage to output comparison result information.

A system for over-the-air testing of a device under test includes a measurement antenna, a reference antenna, a device under test capable of wirelessly transmitting and/or receiving complex radio frequency signals, and an analyzer. The analyzer has at least two ports, wherein the reference antenna is connected with a first port of the analyzer. The measurement antenna is connected with a second port of the analyzer. The analyzer is capable of determining a phase difference and a power ratio of radio frequency signals received via the measurement antenna and the reference antenna. The analyzer is capable of performing an IQ analysis on complex radio frequency signals. Further, a method of over-the-air testing of a device under test is disclosed.

In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.

A method for protecting a reconfigurable digital integrated circuit includes multiple parallel processing channels each comprising an instance of a functional logic block and an error detection unit, the method comprising the successive steps of: activating the error detection unit in order to detect an error in at least one processing channel, executing the data replay mechanism, and then activating the error detection unit in order to detect an error in at least one processing channel, if an error is detected again, executing a self-test on each processing channel, for each processing channel, if the self-test does not detect any error, executing the data replay mechanism for this processing channel, if the self-test detects an error, reconfiguring that part of the configuration memory associated with this processing channel.

In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.

The present disclosure relates to an electronic instrument for analyzing a device-under-test, DUT, comprising: a digital signal generator configured to generate a test signal having a first frequency; a signal output unit which is connected to the DUT, wherein the signal output unit is configured to convert the test signal to an analog signal and to forward said signal to the DUT; a signal input unit which is connected to the DUT and which is configured to receive a DUT response signal which is based on the test signal, wherein the signal input unit is configured to digitalize the DUT response signal; a signal processing circuity configured to receive the digitalized DUT response signal and to downconvert said signal using the first frequency of the test signal; and an analyzing unit configured to analyze the downconverted DUT response signal in order to determine a transfer function, an impedance and/or a loop stability of the DUT.

An apparatus for generating Automatic Test Equipment (ATE) testing patterns to test an electronic device-under-test (DUT) that includes electrical circuitry, at least one input port and at least one output port. The apparatus includes a memory and a processor. The memory is configured to store (i) a high-level verification language (HVL) model of the IC, including a model input that models the at least one DUT input port and a model output that models the at least one DUT output port, the HVL model configured to determine, obliviously to the electrical circuitry, a logic state of the model output responsively to a logic state of the model input, and (ii) a simulation program, configured to simulate the HVL model of the DUT. The processor is configured to generate an ATE testing pattern for the DUT by running the simulation program.

An apparatus includes a processor configured to control an automatic test equipment (ATE) to measure one or more parameters of a current test instance for testing a device under test (DUT), during execution of the current test instance on the DUT, and determine, based on the measured one or more parameters, one or more controls for controlling a temperature of a thermal head connected to the DUT so that a junction temperature of the DUT corresponds to a predetermined test temperature. The processor is further configured to control the temperature of the thermal head, based on the determined one or more controls.

A method and an apparatus for testing a chip, as well as a storage medium, and a chip thereof are provided. The chip includes an operation module. The method includes receiving, via a first pin of the chip, a test control signal indicating a test type of the operation module; performing a first test for the operation module using a first test vector based on the test type; or performing a second test for the operation module using a second test vector, where the first test is a test for the memory included in the operation module and the second test is a test for the functional logic in included in the operation module.

The present disclosure relates to a measurement system for a parallel measurement with multiple tones, comprising: an RF signal source being configured to generate a continuous wave, CW, signal having at least two CW tones, the RF signal source being configured to feed said CW signal to an output port of the system which is arranged for being connected to a device-under-test, DUT; an input port being arranged to receive a response signal from the DUT, the response signal having at least two tones which are based on the at least two CW tones; a conversion unit being configured to convert the response signal to an intermediate frequency, IF, signal by means of analog mixing, thereby converting the at least two tones of the response signal to at least two IF tones; an analog-to-digital converter being configured to convert the IF signal to a digital signal; a parallel processing unit being configured to isolate the at least two IF tones of the IF signal using a digital down conversion, DDC, technique; the parallel processing unit being further configured to perform a measurement on the at least two CW tones and the at least two IF tones to determine at least one scattering parameter of the DUT.