An apparatus includes a processor configured to control an automatic test equipment (ATE) to measure one or more parameters of a current test instance for testing a device under test (DUT), during execution of the current test instance on the DUT, and determine, based on the measured one or more parameters, one or more controls for controlling a temperature of a thermal head connected to the DUT so that a junction temperature of the DUT corresponds to a predetermined test temperature. The processor is further configured to control the temperature of the thermal head, based on the determined one or more controls.

Methods of producing augmented probe system images and associated probe systems. A method of producing an augmented probe system image includes recording a base probe system image, generating the augmented probe system image at least partially based on the base probe system image, and presenting the augmented probe system image. The augmented probe system image includes a representation of at least a portion of the probe system that is obscured in the base probe system image. In some examples, a probe system includes a chuck, a probe assembly, an imaging device, and a controller programmed to perform methods disclosed herein.

Presented embodiments facilitate efficient and effective diagnostic of test system operations, including temperature control of test equipment components. In one embodiment a test equipment diagnostic method includes applying a known/expected first bit pattern to a test equipment component, applying a known/expected second bit pattern to a test equipment component, and performing a test equipment temperature control analysis based upon the results of applying the known/expected first bit pattern and known/expected second bit pattern. The first bit pattern and second bit pattern have known/expected respective thermal loads and corresponding respective first known/expected/expected temperature and second known/expected/expected temperature. In one embodiment, performing a test equipment temperature control analysis includes determining if temperature control components control a temperature of the test equipment component within acceptable tolerances. In one exemplary implementation, the test equipment component is a test control component (e.g., a field programmable gate array (FPGA), etc.).

A system for over-the-air testing of a device under test includes a measurement antenna, a reference antenna, a device under test capable of wirelessly transmitting and/or receiving complex radio frequency signals, and an analyzer. The analyzer has at least two ports, wherein the reference antenna is connected with a first port of the analyzer. The measurement antenna is connected with a second port of the analyzer. The analyzer is capable of determining a phase difference and a power ratio of radio frequency signals received via the measurement antenna and the reference antenna. The analyzer is capable of performing an IQ analysis on complex radio frequency signals. Further, a method of over-the-air testing of a device under test is disclosed.

Generally discussed herein are systems, devices, and methods for device verification. A method can include providing, by test equipment (TE), electrical stimulus consistent with a challenge of a challenge response pair (CRP) to a physical unclonable function (PUF) of a device under test (DUT), receiving, by the TE and from the DUT, a response to the electrical stimulus, comparing, by the TE, the provided response to responses to CRPs in a database including PUF CRPs associated with a device identification and a device type, and validating the identity of the DUT when the response of the PUF to the electrical stimulus matches the response of the CRP or invalidating the identity of the electrical device when the response of the PUF does not match the response of the CRP.

A battery emulation apparatus for supplying a device-under-test (DUT) with electrical power, comprising output terminals for connecting the DUT and an output voltage module providing a variable DC output voltage. A user interface receives a user input comprising the setting of battery parameter(s) and measurement criteria. A data storage stores data representing battery models. A processor selects a battery model based on the parameter(s) and controls the output voltage module to emulate characteristics of the selected battery model(s) according the data, while supplying the DUT with the output voltage. The processor monitors a response of the DUT and/or the output voltage module to the emulated characteristics of the selected battery model(s), wherein the response comprises a physical measurement value. The processor evaluates said physical measurement value based on the set measurement criteria in order to assess the suitability of the selected model(s).

The invention concerns a circuit for transferring a data from one clock domain to another clock domain, the circuit comprising: a digital circuit configured to generate a data signal synchronized with a source clock signal, and to receive such data by sampling the data signal synchronized with a target clock signal; a phase comparator which is configured to determine a phase relationship between the source clock signal and the target clock signal; and a data signal synchronization circuit configured to receive data signal transitions that are synchronized with the source clock signal, and to provide a synchronized data signal transitions of which are synchronized with the target clock signal.

Embodiments of the present disclosure provide a test method and apparatus for a control chip, and an electronic device, which relate to the field of semiconductor device test technologies. The control chip includes a built-in self-test BIST circuit. The method is performed by the BIST circuit. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.

An automated testing machine with data processing function and an information processing method thereof are introduced. The automated testing machine includes a test head for testing more than one device under testing (DUT), and the test head further includes a test processing unit for providing more than one electrical test signal to the DUTs and conducting a processing and analyzing on more than one electrical feedback data fed back from the DUTs, so as to generate analysis result information. With the test processing unit capable of conducting data processing directly provided in the test head, signals obtained from the DUTs can be directly analyzed and processed to enable increased data processing efficiency, increased convenience in use and reduced costs of the automated test machine and the information processing method thereof.

A test and measurement device includes an input for receiving a test waveform from a Device Under Test (DUT), where the test waveform has a plurality of input level transitions, a selector structured to respectively and individually extract only those portions of the test waveform that match two or more predefined patterns of input level transitions of the test waveform, a noise compensator structured to individually determine and remove, for each of the extracted portions of the waveform, a component of a jitter measurement caused by random noise of the test and measurement device receiving the test waveform, a summer structured to produce a composite distribution of timing measurements with removed noise components from the extracted portions of the test waveform, and a jitter processor structured to determine a first noise-compensated jitter measurement of the DUT from the composite distribution. Methods of determining noise-compensated jitter measurements are also disclosed.