A component die validation built-in self-test (VBIST) engine is presented. In an aspect, a component die includes component circuitry for performing a component function, interface circuitry for communicating with another die, and a VBIST circuit. The VBIST circuit includes a traffic generator that generates test data streams, a tracker that receives and validates test data streams, and a configurable switching matrix for coupling the traffic generator to at least one of the component circuitry, the interface circuitry, or the tracker, and for coupling at least one of the component circuitry, the interface circuitry, or the traffic generator to the tracker. The VBIST circuit can send traffic to and from the component circuitry directly, or indirectly via the interface circuitry in loopback mode, and can be used for memory initialization and test.

A measurement system for determining a phase and amplitude influence of a device under test, comprising a measurement instrument having a signal generator, a local oscillator, a first mixer and an analysis unit is disclosed. The signal generator is configured to generate a source signal with a predetermined source frequency and a source phase, and to forward the source signal to the device under test, wherein the source signal is altered by the device under test in at least one of amplitude and phase, such that a measurement signal is generated and forwarded to the first mixer. The local oscillator is configured to generate a local oscillator signal with a predetermined local oscillator frequency and a local oscillator phase, and to forward the local oscillator signal to the first mixer. The first mixer is configured to mix the measurement signal and the local oscillator signal, thereby generating a first mixer signal. The analysis unit is located downstream of the first mixer and is configured to analyze the first mixer signal or a processed version of the first mixer signal. The measurement instrument is configured to perform at least two measurements of the phase and amplitude influence of the device under test by analyzing the first mixer signal or the processed version of the first mixer signal, wherein at least one of the source phase and the local oscillator phase is altered between the at least two measurements.

An automated testing machine with data processing function and an information processing method thereof are introduced. The automated testing machine includes a test head for testing more than one device under testing (DUT), and the test head further includes a test processing unit for providing more than one electrical test signal to the DUTs and conducting a processing and analyzing on more than one electrical feedback data fed back from the DUTs, so as to generate analysis result information. With the test processing unit capable of conducting data processing directly provided in the test head, signals obtained from the DUTs can be directly analyzed and processed to enable increased data processing efficiency, increased convenience in use and reduced costs of the automated test machine and the information processing method thereof.

Generally discussed herein are systems, devices, and methods for device verification. A method can include providing, by test equipment (TE), electrical stimulus consistent with a challenge of a challenge response pair (CRP) to a physical unclonable function (PUF) of a device under test (DUT), receiving, by the TE and from the DUT, a response to the electrical stimulus, comparing, by the TE, the provided response to responses to CRPs in a database including PUF CRPs associated with a device identification and a device type, and validating the identity of the DUT when the response of the PUF to the electrical stimulus matches the response of the CRP or invalidating the identity of the electrical device when the response of the PUF does not match the response of the CRP.

A test and measurement device having a signal source, including an impairment generator configured to output an impairment and a waveform synthesizer. The waveform synthesizer receives an input digital signal to be synthesized, receives the impairment, and synthesizes a synthesized digital signal based on the input digital signal and the impairment. The test and measurement instrument also includes a fixed sample rate digital-to-analog converter configured to receive a clock signal and the synthesized digital signal and output an analog signal.

A method includes receiving tester configuration data, test pattern data, and tester operation data; configuring a circuit for performing a designated test evaluation; generating a stimulus waveform; converting the stimulus waveform to an analog stimulus signal; transferring the analog stimulus signal to a first terminal of a MTJ DUT at reception of a trigger timing signal; generating time traces based on the trigger timing signal; generating a response signal at a second terminal of the MTJ DUT and across a termination resistor as the analog stimulus signal is transferred through the MTJ DUT; converting the response signal to a digitized response signal indicating its voltage amplitude; and performing the designated test evaluation and analysis function in the configurable circuit based on voltage amplitudes and time values of the stimulus waveform, the digitized response signal, and the timing traces.

Techniques include configuring a sequential circuit monitor having been generated by applying a quantifier elimination to each random bit position of random inputs associated with a formal verification driver and selecting a value for random inputs to drive a next stage logic of sequential circuit simulation monitor, a state of the next stage logic being used by sequential circuit simulation monitor to generate sequential inputs to match those permitted by formal verification driver, formal verification driver being specified for a DUT input interface. An equivalence check between sequential circuit simulation monitor and original formal driver matches the same set of sequential inputs permitted original formal driver. The sequential circuit simulation monitor is coupled to a simulation environment and the DUT in simulation environment, sequential circuit simulation monitor being configured to flag an input sequence from the simulation environment not permitted by formal verification driver based on the sequential inputs.

Embodiments of the present invention provide systems and methods for automatically performing TDR calibration to compensate for the time delay of a signal carried over a transmission environment (e.g., cable or other electrical path) used during DUT testing. A signal provider generates a signal along a signal path, and a circuit comprising a capacitor coupled to the signal provider and a diode coupled to the capacitor receives the signal periodically. A measurement unit coupled to the capacitor and the diode measures a voltage at the capacitor to determine a signal characteristic value of the signal along the signal path. The signal characteristic value is used to determine the electrical length (delay) of the transmission environment. TDR calibration is performed using the electrical length to compensate for the time delay/reflections over the transmission environment during testing. Advantageously, embodiments do not use a comparator circuit or a receiver circuit, and therefore can perform TDR calibration without significantly reducing the bandwidth of the testing equipment.

An apparatus for determining a single decision function is configured to obtain measurements from a plurality of devices under test corresponding to stimulating signals applied to the plurality of devices under test. The stimulating signals correspond to a set of tests performed on the plurality of devices under test. The apparatus may further determine a subset of tests from the set of tests, such that the subset of tests is relevant for indicating whether the plurality of devices under test pass the set of tests. The apparatus may also determine the single decision function applicable to measurements from an additional device under test tested using the subset of tests, such that the single decision function is adapted to predict a test result for the set of tests on the basis of the subset of tests.

In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.