A control system, that includes a primary controller and various auxiliary controllers, is configured to facilitate a built-in self-test (BIST) of a system-on-chip (SoC). The primary controller is configured to initiate a BIST sequence associated with the SoC. Based on the BIST sequence initiation, each auxiliary controller is configured to schedule execution of various self-test operations on various functional circuits, various memories, and various logic circuits of the SoC by various functional BIST controllers, various memory BIST controllers, and various logic BIST controllers of the SoC, respectively. Based on the execution of the self-test operations, each auxiliary controller further generates various status bits with each status bit indicating whether at least one functional circuit, at least one memory, or at least one logic circuit is faulty. Based on the status bits generated by each auxiliary controller, a fault diagnosis of the SoC is initiated.

A setup time and hold time detection system including a monitoring unit and a processing unit. The monitoring unit is configured to detect multiple setup times and multiple hold times of multiple test circuits through a source clock signal. The processing unit is configured to record multiple setup times and multiple hold times as multiple detection data. The processing unit is further configured to select a first part of the detection data as multiple first detection data to establish an estimation model. The processing unit is further configured to select a second part of the detection data as multiple second detection data, and compare the second detection data and multiple estimation results generated by the estimation model to obtain an error value of the estimation model.

Various implementations described herein are related to a method for identifying multi-bank memory architecture having multiple banks including a first bank and a second bank. The method may receive a faulty row address having a faulty bank selection bit, and also, the method may select the first bank or the second bank for row redundancy operations based on the faulty bank selection bit.

Systems, methods, and circuits for determining a duty cycle of a periodic input signal are provided. A delay element is configured to delay the periodic input signal based on a digital control word. A digital circuit is configured to generate a first digital control word used to delay the periodic input signal a first amount of time corresponding to a period of the periodic input signal, generate a second digital control word used to delay the periodic input signal a second amount of time corresponding to a portion of the periodic input signal having a logic-level high value, and generate a third digital control word used to delay the periodic input signal a third amount of time corresponding to a portion of the periodic input signal having a logic-level low value. A controller is configured to determine the duty cycle based on the first, second, and third digital control words.

A system on chip includes a one-time programmable (OTP) memory configured to store secure data, an OTP controller including at least one shadow register configured to read the secure data from the OTP memory and to store the secure data, a power management unit configured to receive an operation mode signal from an external device and to output test mode information indicating whether an operation mode is a test mode according to the operation mode signal and a test valid signal corresponding to the secure data, and a test circuit configured to receive the test mode information from the power management unit, to receive test data from the external device, and to output a scan mode signal and a test mode signal according to the test data and a test deactivation signal, wherein the test deactivation signal corresponds to development state data indicating a chip development state in the secure data.

In one embodiment, an apparatus includes at least one fabric to interface with a plurality of intellectual property (IP) blocks of the apparatus, the at least one fabric including at least one status storage, and a fabric bridge controller coupled to the at least one fabric. The fabric bridge controller may be configured to initiate a functional safety test of the at least one fabric in response to a fabric test signal received during functional operation of the apparatus, receive a result of the functional safety test via the at least one status storage, and send to a destination location a test report based on the result. Other embodiments are described and claimed.

A method of testing a data transmission and reception system comprises sending a test signal from a transmitter (14) of the system to a receiver (12) of the system, and analyzing the received signal. A duty cycle relationship is varied between the test signal and the timing signal used by the receiver of the system, and the effect of the duty cycle variation is analyzed. Varying the duty cycle relationship provides duty cycle distortion (DCD), and this can be considered as a form of embedded jitter insertion. This type of jitter can be measured relatively easily.

A control system, that includes a primary controller and various auxiliary controllers, is configured to facilitate a built-in self-test (BIST) of a system-on-chip (SoC). The primary controller is configured to initiate a BIST sequence associated with the SoC. Based on the BIST sequence initiation, each auxiliary controller is configured to schedule execution of various self-test operations on various functional circuits, various memories, and various logic circuits of the SoC by various functional BIST controllers, various memory BIST controllers, and various logic BIST controllers of the SoC, respectively. Based on the execution of the self-test operations, each auxiliary controller further generates various status bits with each status bit indicating whether at least one functional circuit, at least one memory, or at least one logic circuit is faulty. Based on the status bits generated by each auxiliary controller, a fault diagnosis of the SoC is initiated.

A control system, that includes a primary controller and various auxiliary controllers, is configured to facilitate a built-in self-test (BIST) of a system-on-chip (SoC). The primary controller is configured to initiate a BIST sequence associated with the SoC. Based on the BIST sequence initiation, each auxiliary controller is configured to schedule execution of various self-test operations on various functional circuits, various memories, and various logic circuits of the SoC by various functional BIST controllers, various memory BIST controllers, and various logic BIST controllers of the SoC, respectively. Based on the execution of the self-test operations, each auxiliary controller further generates various status bits with each status bit indicating whether at least one functional circuit, at least one memory, or at least one logic circuit is faulty. Based on the status bits generated by each auxiliary controller, a fault diagnosis of the SoC is initiated.

A setup time and hold time detection system including a monitoring unit and a processing unit. The monitoring unit is configured to detect multiple setup times and multiple hold times of multiple test circuits through a source clock signal. The processing unit is configured to record multiple setup times and multiple hold times as multiple detection data. The processing unit is further configured to select a first part of the detection data as multiple first detection data to establish an estimation model. The processing unit is further configured to select a second part of the detection data as multiple second detection data, and compare the second detection data and multiple estimation results generated by the estimation model to obtain an error value of the estimation model.