A method for determining an etch profile is described. The method includes determining a masking layer profile. Loading information can be determined. The loading information indicates dependence of an etch rate for the masking layer profile on a quantity and pattern of material being etched. Flux information can be determined. The flux information indicates dependence of the etch rate on an intensity and a spread angle of radiation incident on the masking layer profile. Re-deposition information can be determined. The re-deposition information indicates dependence of the etch rate on an amount of material removed from the masking layer profile that is re-deposited back on the masking layer profile. An output etch profile for the layer of the wafer is determined based on the loading information, the flux information, and/or the re-deposition information.

Metrology is performed on a semiconductor wafer using a system with an apodizer. A spot is formed on the semiconductor wafer with a diameter from 2 nm to 5 nm. The associated beam of light has a wavelength from 400 nm to 800 nm. Small target measurement can be performed at a range of optical wavelengths.

A semiconductor structure and a method for managing semiconductor wafer stress are disclosed. The semiconductor structure includes a semiconductor wafer, a first stress layer disposed on and in contact with a backside of the semiconductor wafer, and a second stress layer on and in contact with the first stress layer. The first stress layer exerts a first stress on the semiconductor wafer and the second layer exerts a second stress on the semiconductor wafer that is opposite the first backside stress. The method includes forming a first stress layer on and in contact with a backside of a semiconductor wafer, and further forming a second stress layer on and in contact with the first stress layer. The first stress layer exerts a first stress on the semiconductor wafer and the second stress layer exerts a second stress on the semiconductor wafer that is opposite to the first stress.

An inspection tool comprises an imaging system configured to image a portion of a semiconductor substrate. The inspection tool may further comprise an image analysis system configured to obtain an image of a structure on the semiconductor substrate from the imaging system, encode the image of the structure into a latent space thereby forming a first encoding. the image analysis system may subtract an artifact vector, representative of an artifact in the image, from the encoding thereby forming a second encoding; and decode the second encoding to obtain a decoded image.

A semiconductor device capable of improving the quality of a pixel region, an electronic apparatus including the semiconductor device, and a method for manufacturing the semiconductor device are to be provided. The present technology provides a semiconductor device that includes: a first substrate in which a pixel region including a pixel having a photoelectric conversion unit is formed; and a second substrate in which a logic circuit that processes a signal output from the pixel region is formed, the first substrate and the second substrate being stacked. In the semiconductor device, at least one of marks including a mark to be used in an exposure process during the manufacture of the semiconductor device and/or a mark to be used in an inspection process for the semiconductor device is formed in a first region that is a region between a first scribe region that is a peripheral portion of the first substrate and the pixel region and/or in a second region that is a region between a second scribe region that is a peripheral portion of the second substrate and a region corresponding to the pixel region in the second substrate.

A method for calibrating the alignment of a wafer is provided. A plurality of alignment position deviation (APD) simulation results are obtained form a plurality of mark profiles. An alignment analysis is performed on a mark region of the wafer with a light beam. A measured APD of the mark region of the wafer is obtained in response to the light beam. The measured APD is compared with the APD simulation results to obtain alignment calibration data. An exposure process is performed on the wafer with a mask according to the alignment calibration data.

A method includes depositing an inter-metal dielectric (IMD) layer over a conductive line. A via opening is formed in the IMD layer and directly over the conductive line. A width of the conductive line is greater than a width of the via opening. An overlay measurement is performed. The overlay measurement includes obtaining a backscattered electron image of the via opening and the conductive line and determining an overlay between the via opening and the conductive line according to the backscattered electron image.

The first layer mark and the second layer mark are adapted to be projected onto each other during the lithographic process. The first layer components and the second layer components are adapted to be arranged in a plurality of different overlay configurations, each overlay configuration comprising a number of the plurality of the first layer components and a number of the plurality of the second layer components, and each overlay configuration having a different overlay distance at which each first layer component is arranged in a first direction of an associated second layer component of the second layer components. The method comprises determining an overlay step which represents a difference between the different overlay distances of the plurality of overlay configurations, determining a largest overlay distance, determining the number of first layer components and/or the number of associated second layer components in each overlay configuration.

A method including: determining recipe consistencies between one substrate measurement recipe of a plurality of substrate measurement recipes and each other substrate measurement recipe of the plurality of substrate measurement recipes; calculating a function of the recipe consistencies; eliminating the one substrate measurement recipe from the plurality of substrate measurement recipes if the function meets a criterion; and reiterating the determining, calculating and eliminating until a termination condition is met. Also disclosed herein is a substrate measurement apparatus, including a storage configured to store a plurality of substrate measurement recipes, and a processor configured to select one or more substrate measurement recipes from the plurality of substrate measurement recipes based on recipe consistencies among the plurality of substrate measurement recipes.

A metrology method relating to measurement of a structure on a substrate, the structure being subject to one or more asymmetric deviation. The method includes obtaining at least one intensity asymmetry value relating to the one or more asymmetric deviations, wherein the at least one intensity asymmetry value includes a metric related to a difference or imbalance between the respective intensities or amplitudes of at least two diffraction orders of radiation diffracted by the structure; determining at least one phase offset value corresponding to the one or more asymmetric deviations based on the at least one intensity asymmetry value; and determining one or more measurement corrections for the one or more asymmetric deviations from the at least one phase offset value.