Electron beam overlay targets and method of performing overlay measurements on a target using a semiconductor metrology tool are provided. One target includes a plurality of electron beam overlay elements and a plurality of two-dimensional elements that provide at least one two-dimensional imaging. The plurality of two dimensional elements are an array of evenly-spaced polygonal gratings across at least three rows and at least three columns. Another target includes a plurality of electron beam overlay elements and a plurality of AIMid elements. Each of the electron beam overlay elements includes at least two gratings that are overlaid at a perpendicular orientation to each other. The plurality of AIMid elements includes at least two gratings that are overlaid at a perpendicular orientation to each other.

Disclosed is a method for modeling measurement data over a substrate area and associated apparatus. The method comprises obtaining measurement data relating to a first layout; modeling a second model based on said first layout; evaluating the second model on a second layout, the second layout being more dense than said first layout; and fitting a first model to this second model according to the second layout.

The present disclosure provides a measurement mark, a measurement layout, and a semiconductor structure measurement method. A measurement mark includes a first pattern, a second pattern, and a third pattern, the first pattern includes multiple first marks extending in a first direction and arranged in parallel at intervals in a second direction, the second pattern includes multiple second marks arranged at intervals in a staggered manner, and the third pattern includes multiple third marks arranged at intervals in a staggered manner; in projection of the measurement mark on the substrate, projection of the second mark separates projection of the first mark in the first direction; projection of the second pattern does not overlap with projection of the third pattern, and there is an offset distance between the projection of the third pattern and the projection of the second pattern in a third direction.

Embodiments of this invention provide a measurement map configuration method and apparatus. A wafer to be inspected is provided. The wafer includes a plurality of inspection marks. A first inspection result is obtained based on a first set of inspection marks. A second set of inspection marks is selected based on a preset rule. The second set of inspection marks is less than the first set of inspection marks. A second inspection result is obtained based on the second set of inspection marks. If an overlay accuracy of the second inspection result matches an overlay accuracy the first inspection result, a measurement map for the wafer is set based on target inspection marks. The target inspection marks are the second set of inspection marks of the measurement map.

A method for generating metrology sampling scheme for a patterning process, the method including: obtaining a parameter map of a parameter of a patterning process for a substrate; decomposing the parameter map to generate a fingerprint specific to an apparatus of the patterning process and/or a combination of apparatuses of the patterning process; and based on the fingerprint, generating a metrology sampling scheme for a subsequent substrate at the apparatus of the patterning process and/or the combination of apparatuses of the patterning process, wherein the sampling scheme is configured to distribute sampling points on the subsequent substrate so as to improve a metrology sampling density.

The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.

Embodiments of the present disclosure relate to the field of semiconductors, and provide a process recipe, a method and a system for generating same, and a semiconductor manufacturing method. The method for generating a diffraction-based process recipe includes: providing a basic process recipe, the basic process recipe is used to form an initial alignment pattern; and performing a feedback correction step for at least one time to adjust the basic process recipe and obtain an actual process recipe, which each time includes: obtaining a first pattern and a second pattern based on the basic process recipe prior to a current feedback correction step, the first pattern is the initial alignment pattern that is developed, the second pattern is the initial alignment pattern that is etched; and adjusting the basic process recipe prior to the current feedback correction step based on a difference between the first pattern and the second pattern.

A self-calibrating overlay metrology system may receive device overlay data for a device targets on a sample from an overlay metrology tool, determine preliminary device overlay measurements for the device targets including device-scale features using an overlay recipe with the device overlay data as inputs, receive assist overlay data for one or more assist targets on the sample including device-scale features from the overlay metrology tool, where at least one of the one or more assist targets has a programmed overlay offset of a selected value along a particular measurement direction, determine self-calibrating assist overlay measurements for the one or more assist targets based on the assist overlay data, where the self-calibrating assist overlay measurements are linearly proportional to overlay on the sample, and generate corrected overlay measurements for the device targets by adjusting the preliminary device overlay measurements based on the self-calibrating assist overlay measurements.

Multilayered product structures are formed on substrates by a combination of patterning steps, physical processing steps and chemical processing steps. An inspection apparatus illuminates a plurality of target structures and captures pupil images representing the angular distribution of radiation scattered by each target structure. The target structures have the same design but are formed at different locations on a substrate and/or on different substrates. Based on a comparison of the images the inspection apparatus infers the presence of process-induced stack variations between the different locations. In one application, the inspection apparatus separately measures overlay performance of the manufacturing process based on dark-field images, combined with previously determined calibration information. The calibration is adjusted for each target, depending on the stack variations inferred from the pupil images.

Methods and systems for performing overlay and edge placement errors based on Soft X-Ray (SXR) scatterometry measurement data are presented herein. Short wavelength SXR radiation focused over a small illumination spot size enables measurement of design rule targets or in-die active device structures. In some embodiments, SXR scatterometry measurements are performed with SXR radiation having energy in a range from 10 to 5,000 electronvolts. As a result, measurements at SXR wavelengths permit target design at process design rules that closely represents actual device overlay. In some embodiments, SXR scatterometry measurements of overlay and shape parameters are performed simultaneously from the same metrology target to enable accurate measurement of Edge Placement Errors. In another aspect, overlay of aperiodic device structures is estimated based on SXR measurements of design rule targets by calibrating the SXR measurements to reference measurements of the actual device target.